近年來，自旋轉移力矩隨機存取記憶體(STT-RAM)、相變隨機存取記憶體(PCRAM)等非揮發性記憶體(NVM)，因為其低耗能及高密度的特色而受到相當大的重視。但是，NVM同時也有著寫入時間長、有限的寫入次數等問題存在。因此，許多SRAM混合NVM的快取記憶體架構(hybrid cache)被提出，配合上適當的快取寫入管理方針來降低非揮發性記憶體的寫入壓力。
這篇論文考慮到在多核心架構下的hybrid L2 cache會因為不均勻的寫入分布，而導致不均勻的耗損。因此，我們提出了一種由SRAM bank，STT-RAM bank，以及混和SRAM跟STT-RAM的hybrid bank等所組成的混合式快取記憶體架構。基於這個架構，兩個快取寫入管理方針被提出來降低STT-RAM上的寫入壓力。接著，我們提出一個動態切割演算法來動態地分配hybrid L2 cache給每個處理器使用，藉此達到耗損均勻的目的。此外，我們還分析在不同SRAM跟STT-RAM的比例下，hybrid bank對耗損均勻改善的影響變化。
實驗結果顯示，藉由使用提出的快取寫入管理方針及動態切割演算法，我們提出的混合式快取記憶體平均可以改善89倍的使用時間，同時與傳統的SRAM 快取記憶體相比，平均可以省下58%的能量消耗。

Abstract—In recent years, NVM (non-volatile memory) technologies, such as STT-RAM (spin transfer torque RAM) and PRAM (phase change RAM), have drawn a lot of attention due to their low leakage and high density. However, both NVMs suffer from high write latency and limited endurance problems. To mitigate the write pressure on NVM, many SRAM/NVM hybrid cache designs have been proposed with write management policies. Unfortunately, existing hybrid cache design does not consider the unbalanced workload of each core in CMP (chip multi-processors) architecture, resulting in unbalanced wear-out of hybrid cache.
This paper considers the unbalanced write distribution of hybrid cache for CMP architecture, and a novel hybrid cache design that includes SRAM cache, STT-RAM cache, and STT-RAM/SRAM hybrid cache banks is proposed. Based on the proposed hybrid cache design, two access-aware policies are proposed to mitigate unbalanced wear-out of STT-RAM region, and a wearout-aware dynamic cache partitioning scheme is proposed to dynamically partition the hybrid cache, improving the unbalanced write pressure among different cache partitions. Experimental results show that, our proposed scheme and policies can achieve an average of 89 times improvement in cache lifetime and are able to save 58% energy consumption compared to SRAM cache.

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