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研究生： 詹登超
CHAN, Teng-Chao
論文名稱： 使用記憶體配置技術於週期性之應用中以達節能之目的
Using Memory Allocation Technique on Periodic Applications to Reduce Power Consumption
指導教授： 楊竹星
Yang, Chu-Sing
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 中文
論文頁數： 45
中文關鍵詞： 記憶體 、週期性
外文關鍵詞： memory, periodic
相關次數： 點閱：96  下載：3 
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    • 在嵌入式系統省電的議題中，利用記憶體列 (memory bank)為基礎的研究已越來愈多，為了在嵌入式裝置上能夠更加的省電，不論是在硬體層、軟體層、甚至在於編譯器的層面，相關的研究持續的不斷被提出。通常在記憶體列使用上，擁有多種的模式可以利用。使用記憶體列(memory bank)的優勢在於，當某記憶體列不需使用時，可將其模式調整為關閉模式。若此記憶體列需要被存取，則調整為啟動模式。所以在此篇研究，我們藉由準確的預測週期性的程式生命週期，預測程式存取記憶體的時間，進而將靜態隨機記憶體裝置的功率消耗節省到最低，為了達到此目的，我們也設計了ㄧ個模擬環境針對記憶體做適當的配置，並將相關的成果呈現。

    Banked memories have been the focus of several recent efforts that attempt to reduce power consumption and have been studied from both the hardware and software. In order to minimize the energy consumed by the main memory in embedded system, several solutions are proposed. The main advantage in this approach is the capability of independently setting memory banks in shutdown modes. When they are not accessed, only the accessed bank is maintained in online mode. In this research we investigate how this power management capability into SRAM devices can be handled for periodic task application. To achieve this, we design the simulate environment for memory allocation and show the effectiveness.

    第一章 緒論.......................................................................................................................................9 1.1 研究背景與動機...................................................................................................................9 1.2 實作系統簡介.......................................................................................................................9 1.3 章節提要.............................................................................................................................10 第二章 背景知識介紹...................................................................................................................... 11 2.1 PAC PMP SoC 雙核心處理器介紹..................................................................................... 11 2.1.1 PAC PMP SoC 雙核心處理器相關系列................................................................ 11 2.1.2 PAC PMP SoC 的演化......................................................................................... 11 2.1.3 以PAC PMP SoC 為核心之發展平台...................................................................12 2.1.4 PAC PMP SoC 架構介紹........................................................................................13 2.2 ELF 提要.............................................................................................................................18 2.2.1 Object File 與 Elf Format .....................................................................................18 2.2.2 ELF 組成.................................................................................................................19 2.3 ADS 介紹.............................................................................................................................21 2.4 SRAM 提要..........................................................................................................................25 第三章 記憶體節能系統設計........................................................................................................28 3.1 嵌入式運算面臨性能障礙.................................................................................................28 3.2 SRAM 的耗電因素...............................................................................................................31 3.3 系統設計架構....................................................................................................................32 3.4 Scatter Loading..............................................................................................................34 3.4.1 Link Control File..............................................................................................35 3.4.2 何時使用scatter file.......................................................................................36 3.5 急驟電流的問題................................................................................................................37 第四章 記憶體節能系統之建構與模擬........................................................................................39 4.1 模擬環境建構....................................................................................................................39 4.2 記憶體節能系統模擬........................................................................................................42 第五章 結論與未來展望................................................................................................................44 5.1 結論.................................................................................................................................44 5.2 未來工作與展望..............................................................................................................45 參考文獻及資料................................................................................................................................46

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    [14] ITRI PMP_SoC_Memory_Map.pdf
    [15] “Using ld”
    http://ftp.iasi.roedu.net/mirrors/openwrt.org/people/mbm/reference/ld.pdf
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    [17] “Dynamic Voltage Scaling on a Low-Power Microprocessor”, Proceedings of the 7th annual international conference on Mobile computing and network.

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