隨著半導體製程的微細化與環保議題受到大眾的重視，使得低功耗的電路設計成為IC設計產業必然的發展方向。為了降低電路的功耗，在90年代提出了動態調整電壓頻率(Dynamic voltage and frequency scaling，DVFS)的控制方法，動態調整電壓頻率控制透過許多不同的方式(例如:排程規劃、測試樣本、偵測電路..等等)來作為調整電壓頻率的目的，本篇論文探討一斬新的偵測電路。

時序錯誤檢測(Timing-Error Detection)為一個動態偵測技術，透過偵測電路的輸出訊號作為電路操作的判斷指標，雖然此技術能夠有效的降低保證區間，但是時序錯誤檢測技術只能判斷電路是否發生錯誤，不能檢測出離錯誤的操作尚餘多少空間，所以時序錯誤檢測技術只能透過錯誤與否的判斷來調整電壓頻率。當電路偵測到錯誤時必須使系統重置(recovery)，而系統的重置會產生額外的能量消耗，所以如何動態偵測並避免錯誤發生即為本篇論文的研究方向。本論文的電路設計是基於時序錯誤檢測之動態偵測技術，並發展多個區間的偵測。透過多個區間的所偵測到的電路狀態，可提供動態調整電壓頻率控制器做為電路判斷的指標，使得電路能夠操作在一個無錯誤發生且低功耗的操作環境。

With the advances of the semiconductor process and more attention to the environmental issues, low power design becomes a popular strategy for IC design industry. There are different methods, such as schedule planning, test pattern, detection circuit, et al.. Among them, detection circuit is an efficient scheme.

Dynamic voltage and frequency scaling (DVFS) was proposed in the 1990s to decrease the power consumption in large digital systems. . Timing-error detection is a dynamic detection technology. Thanks to the timing-error detection, the output voltage of regulator can be adjusted based on the outputs of the detection circuit. The technology can efficiently decrease the margin and the restriction on minimum path delay. However, the detection technology sometimes makes an error. .When an error appears, the system needs to be reset and consumes some power. Thus, our research focuses on how to dynamically detect the timing error and avoids its occurrence.

The circuit design in this thesis is based on the timing-error detection technology and it is extended to multi-margin detection. With multi-margin detection, the detected circuit states can be used to adjust the voltage and frequency dynamically. Thus, it makes the circuit operate under low-power consumption and zero error rate.

[1] 楊維斌, 動態調整電源店家與操作頻率以降低系統晶片之功率消耗", 系統晶片001期,工研院系統晶片技術發展中心,pp. 130-137.
[2] K. Nowka, A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling", IEEE J. Solid-State Circuits, Nov. 2002.
[3] S. Rangan, N. Mielke, and E. Yeh, Universal recovery behavior of negative bias temperature instability", Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International , pp. 14.3.1- 14.3.4, Dec. 2003.
[4] A.M. Yassine et al., Time dependent breakdown of ultrathin gate oxide", IEEE Trans. Electron Devices, pp. 1416{1420, Jul. 2000.
[5] S. Das et al., A self-tuning DVS processor using delay-error detection and cor- rection", IEEE J. Solid-State Circuits, pp. 792{804, Apr. 2006.
[6] D. Bull et al., A Power-E cient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation", IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 18-31, Jan. 2011.
[7] A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Ngyugen, N. James, and M. Floyd, A distributed critical-path timing monitor for a 65 nmhigh- performance microprocessor," IEEE ISSCC Dig., pp. 398{399, Feb. 2007.
[8] National Institute of Standards and Technology, Speci cation for the Advanced encryption Standard(AES)", FIPS PUB197, Nov. 2001.
[9] O.J. Hernandez, T. Sodon, and M. Adel, Low-Cost Advanced Encryption Stan- dard (AES) VLSI Architecture: A Minimalist Bit-Serial Approach", Proceedings of IEEE SoutheastCon, pp. 121- 125, Apr. 2005.
[10] Xinmiao Zhang, Student Member, IEEE, and Keshab K. Parhi, High-speed VLSI architectures for the AES algorithm", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, no.9, pp.957-967, Sept. 2004.
[11] S. Morioka and A. Satoh, A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, no.7, pp.686-691, July 2004.
[12] W. Kim, M.S. Gupta, G.Y. Wei and D. Brooks, System level analysis of fast, per- core DVFS using on-chip switching regulators", IEEE International Symposium on High Performance Computer Architecture, pp.123-134, Feb. 2008.