近年來隨著物聯網與人工智慧高速發展，需要運算大量的資料。同時，為了減少網路傳輸、注重隱私並加快AI推測速度，邊緣運算裝置的需求隨之提高。在邊緣裝置中，低延遲與低功耗都是不可或缺的條件。在傳統的馮紐曼電腦架構中，因為資料計算時，需要搬運資料往返於中央處理器與記憶體，而消耗大量能量與時間。於是各界開始尋求高速且低功耗的記憶體中運算架構。由記憶體組成的記憶體陣列，可將計算與儲存同時進行達成「記憶體內運算」，並具備平行化處理大量矩陣運算的能力， 成為近年來熱門的研究項目。然而，除了低功耗的優勢外，記憶體內運算是否能滿足運算過程中低延遲的要求，是其能否實用化的關鍵。本篇論文旨在探討讀寫速度相對快速的靜態隨機存取記憶體特性，並利用結構設計與最佳化權重分布的方式提高運算速度，最後與Google TPU提出之脈動陣列進行比較。
本篇論文透過以SystemC/C++為基礎寫成的記憶體行為模擬器，利用結構設計與權重分布最佳化，加速其運算Convolution所需的時間。並同時透過SystemC模擬脈動陣列運算Convolution的狀況。此外，將脈動陣列及記憶體內運算之數位電路部分以Verilog實現並計算其面積與功耗，以比較靜態隨機存取記憶體之記憶體內運算處理核心相對於脈動陣列之優勢。

With the rapid development of Internet of Things and artificial intelligence in recent years, the need to compute large amounts of data has increased. At the same time, the need for edge computing devices has increased in order to reduce network traffic, focus on privacy and speed up AI predictions. Low latency and low power consumption are essential in edge devices. In the traditional von Neumann architecture, data computation consumes a lot of energy and time because of the need to move data between the central processing unit and the memory. This has led to a search for high-speed and low-power computing architectures. A new computational approach named computing-in-memory (CIM) is adopted using memory arrays by simultaneously computing and storing, as well as handling large arrays in parallel. However, apart from the advantage of low power consumption, the capability of CIM to meet the requirements of low latency in edge computing is one of the critical factors for its practicality. The aim of this thesis is to investigate the characteristics of static-random-access-memory (SRAM) with relatively fast read/write speeds, and to improve the speed of computation by means of structural design and optimized weight mapping. Finally, the result is compared with the systolic array design proposed for the Google TPU.
In this thesis, an SRAM CIM behavior simulator written in SystemC/C++ is implemented. Simultaneously, structural design and weight mapping optimization is used to speed up the time required for the computation of convolution. This thesis also simulates the systolic array computation of convolution in SystemC. In addition, the digital components of systolic array and CIM are both implemented in Verilog and their area and power consumption calculated to compare the advantages of the processing elements of CIM with those of systolic arrays.

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