3C產品的發展使得人們生活更加便利的同時，所有電子產品都盡可能輕薄短小讓消費者便於攜帶與使用，同時內部元件也必須追求高效能、低成本的趨勢使產品更有競爭力。而晶圓尺寸越大，同一片晶圓上可生產出來的晶片就越多，將可以降低生產成本，晶圓直徑不斷增加與厚度薄化，勢必在製造過程中產生殘留應力與翹曲等問題。翹曲的產生主要來源在於各元件間熱膨脹係數的不同所引起，進而導致產品生產良率低落、可靠度不佳。
本研究為了瞭解晶圓以及晶圓上的TSV (through silicon via)在熱製程下之翹曲情形，透過有限元素法對其進行模擬。本文主要是研究在熱製程下對晶圓的翹曲，首先模擬不同大小晶圓在熱製程下的翹曲，接著在晶圓加上不同材料的薄膜觀察其翹曲的狀況，最後模擬TSV對晶圓翹曲的影響。
由模擬結果可以發現：(1)在單一晶圓方面，溫度越高晶圓的翹曲量越大，且在超過900°C時將產生塑性變形；晶圓尺寸越大，溫度對翹曲量的影響越大。(2)在晶圓對薄膜方面，銅薄膜對影響晶圓之翹曲程度最劇烈，二氧化矽與氮化矽加在銅薄膜上可以降低因銅薄薄造成的翹曲。(3)田口方法結果顯示間距直徑比對擁有TSV結構的晶片來說想翹曲程度最大。

As the size of wafer becomes lager and lager, more dies can be made in single wafer, thus lowering the manufacturing cost. With larger and thinner wafers, wafer warpage can occur during the IC fabrication process due to existence of residual stresses. Warpage might affect yield and reliability. The main reason of warpage is the mismatch of the coefficients of thermal expansion (CTE) between the components.
To figure out how the TSV (through silicon via) and thin film affect wafer warpage in different thermal processes, a finite element method was adopted for analysis in this study. Four models including bare wafers, wafers of different size, wafers with different thin films, and wafers with TSVs were studied.
The simulation results show that a higher temperature will lead to a larger warpage for bare silicon wafers, especially when the temperature is larger than 900°C due to plastic deformation. In addition, the Cu thin film on the wafer will cause even larger warpage; whereas both silicon dioxide and silicon nitride thin films on the wafer can reduce the wafer warpage. Furthermore, through Taguchi method, we found out that ratio between pitch and TSV diameter is the main reason of wafer warpage.

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