銅的擴散阻障層(Copper Diffusion Barrier)材料一直是很熱門的研究題材，主要是為了要滿足摩耳定律(Moores law)，在元件尺寸不斷縮小，元件速度愈來愈快、元件數目愈來愈龐大的情形下，銅的大馬士革(damascene)製程技術已被用來取代傳統的鋁製程來解決日益嚴重的電阻-電容時間遲滯效應(R-C time delay)。銅雖然有很低的電阻率，但其對介電質層(Dielectric)有很高的移動性與反應性，且對介電質層的附著力也不佳，以上的種種缺點，導致電性測試失效，故不得不在銅與介電質層之中加入一層擴散阻障層。
近幾年除了普遍被業界使用的鉭/氮化鉭(Ta/TaN)之外，另外氮化鎢(WNx)、氮化矽鎢(WSiN)、釕(Ru)、鎢化鈷硼(磷)(CoWB(P))等較新的材料也都廣泛的被研究其對銅阻障的特性。其中，釕有較低的電阻率(約7.1μΩ-cm)與其對銅有良好的附著力、低溶解度，受到了各界的關注，尤其是釕可以直接取代銅之晶種層，可直接在釕擴散阻障層上電鍍銅層，降低電致遷移效應，並節省一道製程步驟。釕雖然有上述諸多優點，但釕阻障層在厚度大於5nm後，其原子晶格排列呈現結晶態(crystalline)，此結構其晶粒邊界(Grain Boundary)會提供銅原子的擴散路徑，所以無法很有效的阻擋銅的擴散。
本論文使用摻雜雜質─磷原子擴散至釕的結晶態的阻障層中，使此雜質有效的填充在釕的晶粒邊界之中，利用雜質來阻擋銅擴散的路徑，以達到改善釕對銅阻障之能力。實驗方法是利用一含有磷的基板來當做磷的來源，先利用高溫擴散的方式，將磷原子摻雜擴散至釕阻障層中，研究其含有磷的釕阻障層，再沈積銅後，在高溫中探討磷原子是否可以有效的將釕之晶粒邊界阻塞住並提升釕阻障層對銅的阻障效果。
研究結果發現，有先擴散磷原子至釕的阻障層，在高溫的熱穩定測試中，比未摻入磷的釕阻障層對銅的阻障效果要來的好，也有較佳的表面粗糙度。因此，磷擴散至釕阻障層中，確實可以改善釕對銅的阻障效果。

Recently, as the device scaling down, in order to meet the Moore’s law, the study of Copper Diffusion Barrier material was widely investigated. The traditional Al process was replaced to Cu dual damascene process to solve RC delay issues. Unfortunately, even the copper provides lower resistivity, but many issues such as reaction with dielectric, high mobility and poor adhesion would result in reliability failure. Therefore, adding a diffusion barrier was a very critical factor to enhance the reliability performance.
Many kinds of diffusion barriers were widely investigated the property of resistant to copper penetration such as Ta/TaN, WNx and Ru. The Ru owns lower bulk resistivity and excellent adhesion with copper layer could be a potential candidate as copper diffusion barrier. Moreover, the solubility between copper and Ru was very low leading to lower inter-diffusion each other. Especially, the Ru diffusion barrier could also replace the PVD copper seed layer and directly electroplated copper layer. But, the thickness of Ru diffusion barrier was less than 5nm, the thin film present crystalline phase leading to copper penetration. The crystalline structure consists of lots of grain boundary which provided fast through path and also could not resistant to copper diffusion.
In this thesis, the impurities stuffy in grain boundary of Ru could block the copper diffusing into dielectric. The impurities stuffy could enhance the thermal property of copper diffusion barrier. We focused on P doping into Ru diffusion barrier to observe its copper blocking capability.
The AES depth profiling shows phosphorous doping into Ru could improve the blocking copper penetration. The impurity such as phosphorous diffusion into Ru may be a good solution for improved Ru copper barrier.

[1]BAN P. WONG, ANURAG MITTAL Nano-CMOS Circuit and Physical Design, Wiley
[2]ITRS 2006
[3]Liu CS, Chen LJ et al. J Appl Phys (1993)
[4]R.J.O.M. Hoofman, G.J.A.M. Verheijden et al. Microelectron. Eng. (2005) 337-344
[5]W.F.A. Besling et al., Microelectron. Eng. 76 (2004) 167–174.
[6]M. Brilloue¨t et al., Microelectron. Eng. 83 (2006) 2036–2041.
[7]ITRS 1998
[8]V. Jousseaume et al., in: Proceedings of the 2005 International Interconnect Technology Conference (IITC 2005), p. 60–62.
[9]Shoichi Uno, Kiyomi Katsuyama et al. Thin Solid Films (2006)
[10]Semiconductor international 1998
[11]Paul Shewmon. “Diffusion in solid” (1989)
[12]James A. Cunningham, solid-state technology
[13]Patrick Leduc, Thierry Farjot et al. Microelectronic Engineering (2006)
[14]Sun-Jung Lee, Soo-Geun Lee et al. IITC (2005)
[15]Robin C.J. Wang, C.C. Lee et al. Microelectronics Reliability 1673-1678 (2006)
[16]M.Lane, C.-K. Hu et al. IITC (2006)
[17]Thaddeus B. Massalski Binary Alloy Phase Diagrams ASM International
[18]http://careerchem.com/NAMED/Elements-Discoverers.pdf
[19]Robert B. Ross, Metallic Materials Specification Handbook CHAPMAN&HALL
[20]R. Chan, T. N. Arunagiri, Y. Zhang, O. Chyan, R. M. Wallace, M. J. Kim,and T. Q. Hurdc, Electrochem. Solid-State Lett. 7, G154 (2004)
[21]O. Chyan, T. N. Arunagiri, and T. Panuswamy, J. Electrochem. Soc. 150,C347 (2003)
[22]S. Rossnagel, The Latest in Ru–Cu Interconnect Technology, Solid State Technol. Online article, February (2005)
[23]R. Chan, T.N. Arunagiri, Y. Zhang, O. Chyan, R.M.Wallace,M.J. Kim, T.Q. Hurd, Electrochem. Solid-State Lett. 7 (2004) G154.
[24]J. Tan, X. Qu, Q. Xie, Y. Zhou, G. Ru, Thin Solid Films 504 (2006) 231.
[25]STEPHEN A. CAMPBELL, “The Science and Engineering of Microelectronic Fabrication” OXFORD
[26]H. Bubert and H. Jenett “Surface and Thin Film Analysis” WILEY-VCH
[27]J.M. Walls. “Methods of Surface Analysis:Techniques and Applications” CAMBRIDGE UNIVERSITY PRESS
[28]D.J. O,Connor B.A. Sexton. “Surface Analysis Methods in Materials Science” Springer-Verlag
[29]Yuzhang Liu, Shuangxi Song, Microelectronic Engineering, (2004)