在點一八微米至九十奈米階段的超大型積體電路製程技術中，鈷矽化物與鎢插栓被應用為前段元件與後段導線的連接結構。較之鈦矽化物，鈷矽化物因具有低阻抗、高熱穩定性、與窄線寬效應的免疫力，而被廣泛採用。然而，在點一三微米以後，鈷矽化物形成不易會有表面凹洞與底面突入。這些缺陷造成潛在接面漏電流並消耗大量電力。
又鎳矽化物已被認定為六十五奈米以後的主流材料。相較於鈷矽化物，鎳矽化物的矽反應量較低、且無凹洞與突入。然而，鎳矽化物的熱穩定性較差、容易被氧化或氟化、以及對矽基板污染的敏感度高。
在點一八微米之前，接觸窗與介層窗之填充材料為鎢插栓，而鋁則是金屬導線材料。但當後段製程轉換至銅鑲嵌技術後，因為銅擴散力強並易污染元件，故鎢插栓仍被保留來作接觸窗。然而，鎢會因填充能力差而導致出現裂縫，並伴隨著接觸窗洞口出現針孔，而成為較高接觸電阻與靜態漏電流的主因。此外，最近三年中，擁有均勻且強韌擴散阻障層的銅插栓及一種全新稱為“分子層沉積”的氮化鉭沉積技術，已預期將在六十五奈米以後取代現行介層窗“物理氣相沉積”的氮化鉭。同樣的，它亦可取代現今接觸窗“有機金屬化學氣相沉積”的氮化鈦。
因此吾人在十二吋晶圓上，以點一三微米製程進行鎢插栓及銅插栓接觸窗並研究與鈷矽化物及鎳矽化物之間的交互反應，而得數項結論如下。
第一，由於接觸窗蝕刻與光阻灰化清洗，鎳矽化物容易生成非晶質的氧化鎳或氟化鎳。要改善此問題,要將接觸窗蝕刻分成兩個步驟，並避免鎳矽化物曝露在高密度氧電漿的環境中。此外，在同樣厚度，鎳矽化物的片電阻與接面漏電流均相當接近於鈷矽化物。
第二，將三層次阻障層的銅插栓與鈷矽化物接觸在一起，則接觸電阻遠低於鎢插栓，但在晶圓外緣因具較高的接面漏電流將使改變不具成效。縮短接觸窗額外蝕刻的秒數可以改善此現象，但卻造成接觸電阻不穩定。以鎳矽化物取代鈷矽化物，與三層次阻障層的銅插栓接觸，漏電流將獲得徹底改善，但在接觸點附近鎳矽化物的平整性變差且粗糙度變高。
總之，在十二吋晶圓上進行小於零點一三微米製程，“銅插栓加上鎳矽化物”結構將是改善並取代“鎢插栓加上鈷矽化物”的最佳解決方案

CoSi2 was widely adopted due to its low resistivity, good thermal stability and immunity to narrow line width effect compared with TiSi2. Additionally, Cobalt salicide with Tungsten plug has been developed as bridge structure between front-end devices and back- end interconnects of ULSI technology since 0.18um to 90nm. However, a great deal of surface pits and bottom spikes in CoSi2 were widely found after 0.13um node, which then cause large junction leakage and consume power seriously. On the other hand, Nicole salicide has been investigated as candidate for sub-65nm. The lower silicon consumption, pits and spikes free are the advantages of over CoSi2. However, NiSi still possesses the drawbacks of poor thermal stability, easy to be oxidized or fluorinated and high sensitivity to substrate contamination.
Furthermore, Tungsten was used as contact and via filling material before 0.18um node, but due to the high diffusion of Cu, it was still adopted for contact even as the back-end technology had been switched into Copper damascenes. Nevertheless, seams and contact surface pin holes caused by poor filling of W become the dominator of higher contact resistance and stand-by power leakage. Next, copper plug with conformal and robust barrier were addressed since three years ago. And the new technology “Atomic Layer Deposition” claimed to replace conventional “PVD” for deposition of TaN in sub-65nm. It also could replace conventional “Metal Organic CVD” TiN for sub-0.13um contact plug.
In this thesis, we study the contact reactions among tungsten plug, copper plug, CoSi2 and NiSi with 0.13um process technology on 300mm wafer and reveal several points as follows.
First, most of formed NiOx or NiFx layers are in amorphous type due to the contact etching and strip clean. The problem has been solved by dividing contact etching into two steps to avoid NiSi from exposing to high density Oxygen plasma environment. Additionally, in comparison to CoSi2, both sheet resistance and junction leakage of NiSi are comparable.
Second, contact resistance of Cu plug on CoSi2 with tri-layer barrier is much lower than W plug except in wafer edge, in where higher junction leakage draws back the improvement. A shorten time contact over etching can suppress it, but may cause unstable contact resistance. Next, replacing CoSi2 with NiSi, the Cu plug with tri-layer barrier can be free of leakage but engraving the film uniformity and roughness of NiSi under contact.
In summary, we found the “Cu plug with NiSi” is the most promising structure to replace “W plug with CoSi2” for sub-0.13 um and beyond ULSI technology on 300mm wafers.

﹝1﹞ C.M. Wu, M.Y. Wang, S.L. Shue, C.H.Yu, and M.S. Liang, “Integration of CVD W on MOCVD TiN”, IEEE International Symposium on VLSI technology, System and Applications, pp.261-263, 2001
﹝2﹞ Ardeshir Sidhwa, Chuck Spinner, Todd Gandy, Mike Goulding, William Brown, Hameed Naseem, Richard Ulrich, Simon Ang, Sherwood Charlton, Vinay Prasad, and Tomothy Cale, “Study of the Step Coverage and Contact Resistance by Using Two-Step TiN Barrier and Evolve Simulation”, IEEE Transactions on Semi- conductor Manufacturing, vol.18, no.1, pp.163-173, 2005
﹝3﹞ J.Y. Dai, S. Ansari, C.L. Tay, S.F. Tee, Eddie Er and S. Redkar, “Failure Mechanism study for high resistance contact in CMOS devices”, IEEE Preceedings of 8th IPFA, pp.130-133,2001
﹝4﹞ H. Kawasaki and C.K. Hu, “An ElectroMigration Failure Model of Tungsten Plug Contacts/ Vias for Realistic Lifetime Prediction”, IEEE Symposium on VLSI Technology Digest of Technical Papers, pp.192-193, 1996
﹝5﹞ Liu Jian, Huang Rongxu, Jiang Juxiao, Zheng Guoxiang, “Environment-friendly PVD Al-plug Process for Submicron Multilayer Interconnection”, International IEEE Conference on Asian Green Electronics, pp.92-95, 2004
﹝6﹞ R. Islam, S. Venkatesan, M. Woo, R. Nagabushnam, D. Denning, K. Yu, O. Adetutu, J. Farkas, Tab Stephens and T. Sparks, “A 0.20um CMOS Technology with Copper-filled Contact and Local Interconnect”, Symposium on VLSI Technology Digest of Technical Papers, pp.22-23, 2000
﹝7﹞ M. Inohara, T. Fujimaki, K. Yoshida, K. Miyamoto, T. Katata, J. Wada, A. Sakata, K. Kinoshita and F. Matsuoka, “Copper Filling Contact Process to Realize Low Resistance and Low Cost Production fully compatible to SOC devices”, IEEE Electron Devices Meeting, pp.461-463, 2001
﹝8﹞ K. Musaka, B. Zheng, H. Wang, K. Wijekoon, L. Chen, J. Lin, K. Watanabe, K. Ohira, T. Hosoda, K. Miyata, T. Hasegawa, G. Dixit, R. Chueng, M. Yamada, S. Kadomura, “Thermal Stress and Reliability Characterization of Barriers for Cu Interconnects”, IEEE Proceedings of the International Interconnect Technology Conference, pp.83-85, 2001
﹝9﹞ S.M. Rossnagel and H. Kim, “From PVD to CVD to ALD for Interconnects and Related Applications”, IEEE Proceedings of the International Interconnect Technology Conference, pp.3-5, 2001
﹝10﹞ H. Chung, M. Chang, S. Chu, N. Kumar, K. Goto, N. Maity, S. Sankarana- rayanan, H. Okamura, N. Ohtsuka and S. Ogawa, “An Ultra-Thin ALD TaN Barrier for High-Performance Cu Interconnects”, IEEE International Symposium on Semiconductor Manufacturing, pp.454-456, 2003
﹝11﹞ C.H. Peng, C.H. Hsieh, C.L. Huang, J.C. Lin, M.H. Tsai, M.W. Lin, C.L. Chang, Winston S. Shue, and M.S. Liang, “A 90nm Generation Copper Dual Damascene Technology with ALD TaN Barrier”, IEEE Electron Devices Meeting, pp.603-606, 2002
﹝12﹞ O. van der Straten, Y. Zhu, E. Eisenbraun, A. Kaloyeros, “Thermal and electrical barrier performance testing of ultrathin atomic layer deposition tantalum-based materials for nanoscale copper metallization”, IEEE Proceedings of the International Interconnect Technology Conference, pp.188-190, 2002
﹝13﹞ K. Higashi, H. Yamaguchi, S.Omoto, A. Sakata, T. Katata, N. Matsunaga and H. Shibata, “ Highly Reliable PVD/ALD/PVD Stacked Barrier Metal Structure for 45nm Node Copper Dual-Damascene Interconnects”, IEEE Proceedings of the International Interconnect Technology Conference, pp.6-8, 2004
﹝14﹞ Ken Inoue, Kaoru Mikagi, Hitoshi Abiko, Shinichi Chikaki and Takamaro Kikkawa, “A New Cobalt Salicide Technology for 0.15um CMOS Devices”, IEEE Transactions on Electron Devices, vol.45, no.11, pp. 2312-2318, 1998
﹝15﹞ Ken-ichi Goto, Atsuo Fushida, Junichi Watanabe, Takae Sukegawa, Yoko Tada, Tomoji Nakamura, Tatsuya Yamazaki and Toshihiro Sugii, “A New Leakage Mechanism of Co Salicide and Optimized Process Conditions”, IEEE Transactions on Electron Devices, vol.46, no.1, pp.117-124, 1999
﹝16﹞ Tatsuyo Ohguro, Masanobu Saito, Eiji Morifuji, Takashi Yoshitomi, Toyota Morimoto, Hisayo Sasaki Momose, Yasuhiro Katsumata and Hiroshi Iwai, “IEEE Transactions on Electron Devices, vol.47, no.11, pp.2208-2213, 2000
﹝17﹞ M.Y. Wang, C.W. Chang, C.M. Wu, C.T. Lin, C.H. Hsieh, Winston S. Shue and M.S. Liang, “Novel Co/Ni Bi-layer Salicidation for 45nm Gate Technology”, IEEE Symposium on VLSI Technology Digest of Technical Papers, pp.157-158, 2003
﹝18﹞ K.Suguro, T. Iinuma, M. Izuha, K. Ohuchi, A. Hokazono, K. Miyano and I. Mizushima, “Silicide Technology for USJ in Next Technology Node”, IEEE International Workshop on Junction Technology, pp.67-70,2002
﹝19﹞ Qi Xiang, Christy Woo, Eric Paton, John Foster, Bin Yu and Ming-Ren Lin, “Deep Sub-100nm CMOS with Ultra Low Gate Sheet Resistance by NiSi”, IEEE Symposium on VLSI Technology Digest of Technical Papers, pp.76-77, 2000
﹝20﹞ M.C. Sun, M.J. Kim, J.H. Ku, K.J. Roh, C.S. Kim, S.P. Youn, S.W. Jung, S. Choi, N.I. Lee, H.K. Kang and K.P. Suh, “Thermally Robust Ta-Doped Ni SALICIDE Process Promising for sub-50nm CMOSFETs”, IEEE Symposium on VLSI Technology Digest of Technical Papers, pp.81-82, 2003
﹝21﹞ J.P. Lu, D. Miles, J. Zhao, A. Gurba, Y. Xu, C. Lin, M. Hewson, J. Ruan, L. Tsung, R. Kuan, T. Grider, D. Mercer, C. Montgomery, “A Novel Nickel SALICIDE Process Technology for CMOS Devices with sub-40nm Physical Gate Length”, IEEE Electron Devices Meeting, pp.371-374, 2002
﹝22﹞ P.S. Lee, K.L. Pey, D. Mangelinck, J. Ding, A.T.S. Wee and L Chan, “Improved NiSi Salicide Process Using Presilicide N2+ Implant for MOSFETs”, IEEE Electron Device Letters, vol.21, no.12, pp.566-568, 2000
﹝23﹞ N. Kusunoki, K. Ohuchi, A. Hokazono, N. Aoki, H.. Tanimoto and K. Matsuzawa, “Topography and Schottky Contact Models applied to NiSi SALICIDE Process”, IEEE International Conference on Simulation of Semiconductor Processes and Devices, pp.59-62, 2003
﹝24﹞ Ken-ichi Goto, Junichi Watanabe, Takae Sukegawa, Atsuo Fushida, Takashi Sakuma and Toshihiro Sugii, “A Comparative Study of Leakage Mechanism of Co and Ni Salicide Processes”, IEEE 36th Annual International Reliability Physics Symposium, pp.363-369, 1998
﹝25﹞ B. Froment, M. Muller, H. Brut, R. Pantel, V. Carron, H. Achard, A. Halimaoui, F. Boeuf, F. Wacquant, C. Regnier, D. Ceccarelli, R. Palla, A. Beverina, V. DeJonghe, P. Spinelli, O. Leborgne, K. Bard, S. Lis, V. Tirard, P. Morin, F. Trentesaux, V. Gravey, T. Mandrekar, D. Rabilloud, S. Van, E. Olson and J. Diedrick, “Nickel vs Cobalt Silicide integration for sub-50nm CMOS”, IEEE 33rd Conference of European Solid-State Device Research, pp.215-218, 2003