在本論文中，我們針對中值濾波器提出可模組化設計的硬體架構，可依情況選擇相對應之模組。一般而言，中值濾波器大多是採用字級(word-level)完成硬體實踐，此方式受限於固定的資料寬度，造成較大的面積與較低的效能。在本設計中提出可選擇使用位元級的串接方式，因為位元級有最低複雜度的運算優勢，可以大幅提升執行速度，或是使用部分字級(partial-word-level)串接方法，因為部分字級(partial-word-level)有較少的管線級數與較小的比較資料寬度，可以使用較少的資料暫存器與中值暫存器，來達成低成本高效能之目標。
本論文中，所有硬體架構的實現是使用Verilog HDL，並使用Synopsys Design compiler以及 TSMC 90nm 標準元件庫合成。實驗結果顯示，本論文所提出的設計相較於已存的架構，不只可以減少面積成本，與現有的中值濾波器相比最高降低23%，在運算速度上最快可以達到2000MHz以上的操作頻率。

This dissertation presents a modular design of very large-scale integrated (VLSI) architecture for median filter. Users can select the most suitable module according to their requirements. In the ordinary course of events, the implementation of hardware median filter architecture applies word-level design. However, the performance of conventional median filter architecture is limited by the bit-width of input samples. The resource consumption increases seriously and computation speed gets worse as the data length grows. In the proposed design, we employ the bit-level cascaded architecture to solve the problem. Hardware-oriented optimization is performed by our design in order to improve the performance in terms of operation frequency and area cost.
The proposed designs were implemented by using Verilog HDL and synthesized by Synopsys Design Compiler with TSMC 90mn library. The synthesis results demonstrated that the proposed design has the advantage of low-cost and high-performance. The maximal operation speed achieved 2000 MHz and the resource consumption was reduced by 23.93% when compared to the state-of-the-art architecture.

[1] G. R. Arce, Nonlinear Signal Processing: A Statistical Approach. Hoboken, NJ, USA:Wiley, 2004.
[2] Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest, and Clifford Stein, Introduction to Algorithms, The MIT Press, Third Edition, 2009.
[3] J. Chhugani, A. D. Nguyen, V. W. Lee, W. Macy, M. Hagog, Y.-K. Chen, A. Baransi, S. Kumar, and P. Dubey, “Efficient implementation of sorting on multi-core SIMD CPU architecture,” Proc. VLDB Endow., vol. 1, no. 2, pp. 1313–1324, Aug. 2008.
[4] V. G. Moshnyaga and K. Hashimoto, “An efficient implementation of 1-D median filter,” in Proc. 52nd IEEE Int. MWSCAS, 2009, pp. 451–454.
[5] R.-D. Chen, P.-Y. Chen, and C.-H. Yeh, "Design of an area-efficient one-dimensional median filter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 662–666, Oct. 2013.
[6] E. Nikahd, P. Behnam and R. Sameni, "High-Speed Hardware Implementation of Fixed and Runtime Variable Window Length 1-D Median Filters," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 5, pp. 478-482, May 2016.
[7] D. Prokin and M. Prokin, “Low hardware complexity pipelined rank filter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 446–450, Jun. 2010.
[8] J. O. Cadenas, G. M. Megson and R. S. Sherratt, "Median Filter Architecture by Accumulative Parallel Counters," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 7, pp. 661-665, July 2015.
[9] D. M. Bappy and I. Jeon, "Combination of hybrid median filter and totalvariation minimisation for medical X-ray image restoration," in IETImage Processing, vol. 10, no. 4, pp. 261-271, 4 2016.
[10] Q. Yang et al., "Fusion of Median and Bilateral Filtering for Range ImageUpsampling," in IEEE Transactions on Image Processing, vol. 22, no. 12,pp. 4841-4852, Dec. 2013.
[11] L. A. Aranda, P. Reviriego, and J. A. Maestro, “A Fault-TolerantImplementation of the Median Filter”, Radiation Effects on Componentsand Systems (RADECS) Conference, Bremen, Germany, 2016.
[12] B. Weiss, “Fast median and bilateral filtering,” ACM Transactions onGraphics, vol. 25, no. 3, 2006, pp. 519–526.
[13] Q. Yang, N. Ahuja, and K.-H. Tan, “Constant time median and bilateralfiltering,” Int. J. Comput. Vision, vol. 112, no. 3, pp. 307–318, 2014.
[14] Erl-Huei Lu, Jau-Yien Lee and Yawpo Yang, "VLSI architectures for median filtering with linear complexity," TENCON '96. Proceedings., 1996 IEEE TENCON. Digital Signal Processing Applications, Perth, WA, 1996, pp. 358-362 vol.1.
[15] Charng Long Lee and Chein-Wei Jen, "A bit-level scalable median filter using simple majority circuit," International Symposium on VLSI Technology, Systems and Applications,, Taipei, 1989, pp. 174-177.
[16] J. Das, B. Das, J. Saikia and S. R. Nirmala, "Removal of salt and pepper noise using selective adaptive median filter," 2016 International Conference on Accessibility to Digital World (ICADW), Guwahati, India, 2016, pp. 203-206.
[17] M. A. Gungor and I. Karagoz, "The effects of the median filter with different window sizes for ultrasound image," 2016 2nd IEEE International Conference on Computer and Communications (ICCC), Chengdu, 2016, pp. 549-552.
[18] M. Mukherjee, Kamarujjaman and M. Maitra, "Reconfigurable architecture of adaptive median filter — An FPGA based approach for impulse noise suppression," Proceedings of the 2015 Third International Conference on Computer, Communication, Control and Information Technology (C3IT), Hooghly, 2015, pp. 1-6.
[19] I. Kauppinen, "Methods for detecting impulsive noise in speech and audio signals," 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628), 2002, pp. 967-970 vol.2.
[20] Berlin Database of Emotional Speech [Onilne]. Availablehttp://emodb.bilderbar.info/start.html.