| 研究生: |
劉明穎 Liu, Ming-Ying |
|---|---|
| 論文名稱: |
低複雜度無失真浮水印編碼晶片 A Low Complexity Lossless Watermarking Encoding Chip |
| 指導教授: |
陳培殷
Chen, Pei-yin |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2009 |
| 畢業學年度: | 97 |
| 語文別: | 中文 |
| 論文頁數: | 51 |
| 中文關鍵詞: | 影像認證 、低複雜度硬體實作 、無失真浮水印 |
| 外文關鍵詞: | lossless watermarking, image verification, low complexity hardware implementation |
| 相關次數: | 點閱:108 下載:0 |
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數位認證技術一直是資訊安全的一個重要議題。其中應用在數位影像上的認證最廣泛的便是數位浮水印技術。然而數位浮水印具有嵌入影像的特性,會造成影像失真,這在醫學或軍事影像上是不允許的。因此近年來,無失真的浮水印嵌入技術變成一項熱門的課題。在本論文中,我們會針對一個相當受歡迎的無失真浮水印影像驗證架構提出降低複雜度,提升效能的方法,並將改良後的方法中關於浮水印嵌入的技術以硬體實現。在無失真浮水印部分,我們以簡單的預測編碼法取代原本較複雜的預測編碼法,並調整量化後的差值資訊,以達到最佳的壓縮效率。同時利用變動長度編碼法取代算術編碼法,降低複雜度並增加運算速度。最後,透過統計影像驗證部分的資訊,對變動長度編碼做適應性的調整,改善整體編碼壓縮量與減少變動長度編碼所需的編碼表容量。在影像認證上,利用硬體資源共享及平行處理,實作了計算簽章的雜湊函數,所以在認證的階層式架構上,可以大幅加快運算速度。實驗結果顯示,我們的方法在影像的品質上跟原方法結果相當接近,可嵌入資訊量也有不錯的效果。而提出的硬體架構,根據合成模擬的結果,在 TSMC 0.18μm 製程下,我們的電路可以到達 100MHz的運作速度,在輸入影像大小256×256的情況下,處理效能可達每秒約787張影像。
Digital authentication is an important issue of the information security. Digital watermark, which exploits the redundancy in the image data, is generally used for image authentication. However, some embedding distortion is not allowed in medical and military images. For this reason, lossless data embedding techniques still study widely in recent years. In this thesis, we propose a method to reduce the complexity and improve throughput of a very popular framework of lossless watermarking for image authentication, we also implement watermarking phase of our method in hardware. In lossless watermarking phase, we use a simple predictive coding method to replace original one, and revise the residual after quantization for optimal compression efficiency. Instead of arithmetic coding, we adopt VLC to reduce complexity and improve computing speed. Finally, we count information of verification phase and adjust VLC in adaptive way to improve compression efficiency and cut down the space of coding table. In verification phase, we implement the hash function which computes the signatures in hardware by resource sharing and parallel processing to speed up the verification in hierarchical architecture. Experiment results demonstrate that our method can obtain almost the same image qualities as the original method. Furthermore, the proposed hardware architecture can implement more quickly and efficiently than the original one. According to our simulation, the design can operate at 100 MHz properly with the TSMC 0.18μm technology and process a video resolution of 256×256 at 787 fps.
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校內:2108-07-09公開