氧化鋅薄膜電晶體，因其具有潛力應用於液晶面板上做為驅動與畫素開關的元件，並且可應用在新穎的全透明電路與軟性電子上，己引發熱烈的研究。然而，目前已知的氧化鋅薄膜電晶體仍存在過高的臨界電壓、太大的次臨界擺幅與過大的操作電壓等缺點，使其在應用上仍有限制。這個原因主要是一般的氧化鋅薄膜電晶體使用了低介電係數的材料(例如二氧化矽)作為閘極介電層，因此造成了較差的閘極控制力。為了克服這個低介電閘極所造成的問題，本研究選用high-k材料做為薄膜電晶體之閘極介電層。於眾多高介電係數材料之中，二氧化鉿是一很好的選擇，因其具有高介電係數以及足夠寬的能隙寬度。然而正如其應用在互補式金氧半場效電晶體的缺點一樣，二氧化鉿存在過高的缺陷密度將會阻礙它應用在薄膜電晶體的領域。因此在本論文中，我們在二氧化鉿融入鑭元素以及鈦元素以形成氧化鑭鉿與氧化鈦鉿並且以此兩種高介電係數的化合物作為閘極介電層來製作氧化鋅薄膜電晶體。
在本論文第一部份中，我們主要探討了氧化鋅厚度對薄膜電晶體的特性的影響。我們以氮化鉭作為金屬閘極材料，搭配氧化鑭鉿作為閘極介電層來製作氧化鋅薄膜電晶體。同時製作氮化鉭/氧化鑭鉿/鋁結構的金屬/絕緣層/金屬(Metal-Insulator-metal, MIM)電容來評估氧化鑭鉿的k值與薄膜電晶體之載子遷移率。物性分析方面我們利用X光繞射分析(XRD)、化學分析電子儀(XPS)與掃描式電子顯微鏡(SEM)分析氧化鋅薄膜。經由量測出之5 fF/um^2的電容值與30 nm的物理厚度，我們計算出氧化鑭鉿的k值為25。在實驗中我們發現以沉積時間為一分鐘的氧化鋅通道之元件特性表現最好。電晶體之特性量測包括IDS-VDS和IDS-VGS特性，實驗結果顯示電晶體之開關電流比約為10^5，另由IDS-VGS萃取出臨界電壓約為0.28 V，次臨界擺幅為0.26 V/dec，而通道的載子遷移率為3.5 cm^2/V-sec。
本論文的第二個部份我們以相似的研究架構進行，而在結構上將氧化鑭鉿介電層改為氧化鈦鉿。主要探討不同的介電層沉積後退火處理(Post Deposition Anneal, PDA)的溫度用來評估退火溫度對元件特性的影響。物性分析我們利用X光繞射分析(XRD)、化學分析電子儀(XPS)分析氧化鈦鉿薄膜。經由量測出之7 fF/um^2電容值與50 nm物理厚度，我們計算出氧化鈦鉿的k值為40，比氧化鑭鉿更高，如此高的k值對助於提高元件的驅動電流。實驗結果發現以溫度為500℃之退火處理所獲得的元件特性為最好。電晶體之特性量測包括IDS-VDS和IDS-VGS特性。電晶體之開關電流比約為10^5，另由IDS-VGS萃取出臨界電壓約為0.34 V，次臨界擺幅為0.23 V/dec，而通道的載子遷移率為2.1 cm^2/V-sec。
由實驗結果顯示，以氮化鉭為金屬閘極分別搭配閘極介電層HfLaO與HfTiO的結構，極適用於氧化鋅薄膜電晶體，對於TFT-LCD 的應用深具潛力◦

ZnO-based TFTs have attracted considerable attention due to their potentials toward a new driving and pixel switch component for liquid crystal display and novel applications such transparent and flexible electronics. However, most of ZnO TFTs suffered from high threshold voltage (VT), poor subshreshold swing (SS), and high operation voltage, still setting a limit on their applications. These issues mainly result from the use of low dielectric materials (such as SiO2), which usually leads to poor gate control on the channel current. To overcome the problems originated from using low-k materials, high-k materials need to be adopted as the gate dielectrics for the ZnO TFTs. Among high-k materials, Hafnium oxide (HfO2) was proposed as a good choice for its high dielectric constant and wide bandgap. However, its drawback of high charge trap density as in the CMOS application may retard its further application in the field of TFTs. Therefore, in this thesis, attempts have been made to integrate lanthanum (La) and titanium (Ti) into HfO2 to form HfLaO and HfTiO as the gate dielectrics for the fabrication of ZnO TFTs .
In the first part of the thesis, the influence of different ZnO thicknesses on the TFT characteristics was investigated. Tantalum nitride (TaN) and hafnium lanthanum oxide (HfLaO) were employed as the gate electrode and gate insulator, respectively for ZnO thin film transistors. MIM capacitors with TaN/HfLaO/Al structure were also fabricated to evaluate the dielectric constant of high-kmaterial and device mobility. The physical properties and compositions of ZnO film were confirmed by SEM, XRD, and XPS analysis. From the highest capacitance of 5 fF/um^2 and the physical thickness of 30 nm, we estimated the dielectric of HfLaO was 25. Ids-Vds and Ids-Vgs characteristies of TFTs showed that ZnO deposited for 1 min might be the best condition for the channel layer. The Ion/Ioff ratio, threshold voltage, subthreshold swing, and mobility obtained from the fabricated ZnO-TFTs with TaN(50 nm)/HfLaO(30 nm)/Al(300 nm) structure were 10^5, 0.28 V, 0.26V/dec, and 3.5 cm^2/V-sec, respectively.
In the second part of the thesis, the similar research scheme was applied except the HfLaO was replaced by hafnium titanium oxide (HfTiO) as the gate insulator. Different post deposition annealing (PDA) temperatures for HfTiO gate dielectrics were made to examine the temperature influences on device characteristics. The physical properties and compositions of HfTiO high-k film were also confirmed by XRD and XPS analysis. From the highest capacitance of 7 fF/um^2 and the physical thickness of 50 nm, we estimated this HfTiO dielectric has a even higher k value of 40 than HfLaO which should much benefit the driving current of ZnO TFTs. Experimental results showed the best-behaviored characteristics of ZnO-TFTs were obtained at optimum PDA temperature of 500℃ for HfTiO gate dielectrics. The Ion/Ioff ratio, threshold voltage, subthreshold swing, and mobility obtained from the fabricated ZnO-TFTs with TaN(50 nm)/HfTiO(50 nm)/Al(300 nm) structure were 10^5, 0.34 V, 0.23V/dec, and 2.1 cm^2/V-sec, respectively.
In summary, our detailed preliminary experimental results revealed that both HfLaO and HfTiO gate dielectrics work well for future ZnO-TFTs.

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