先進電子元件中之多層互連結構的主要失效原因之一是由於熱或機械應力所導致的界面脫層。由於這一些互連結構採用了許多新的介電質材料及製程，其受應力下之結構反應相關知識十分缺乏，因此要預測互連結構之可靠度，已成為一大挑戰。為了節省研發所需的成本和時間，必須回到物理基本面找出一個可以解釋界面脫層的物理模型，以預測產品的可靠度。完整的界面脫層物理模型包含界面脫層驅動力之分析，以及脫層破壞韌性之求得，並藉此預測脫層之成長。本論文著重於脫層破壞韌性之求於，內容包含界面脫層破壞韌性實驗之建立及臨界應變能釋放率之量測。本研究首先設計並建立一微拉伸試驗機台，並以模式一形式之雙懸臂樑破壞實驗方式量測界面臨界應變能釋放率。分析的界面為電子構裝結構中常見之聚醯亞胺薄膜與氮化矽薄膜界面、聚醯亞胺薄膜與矽晶界面、以及聚醯亞胺薄膜與金薄膜界面。實驗結果發現聚醯亞胺與氮化矽界面之臨界應變能釋放率十分高，其值約為聚醯亞胺與矽晶界面之臨界應變能釋放率的三倍，此現象可歸因於氮化矽薄膜表面較矽晶表面為粗糙，提供聚醯亞胺較佳之鍵結。另外，聚醯亞胺薄膜與金薄膜界面之臨界應變能釋放率則十分微弱，低於醯亞胺與矽晶界面之臨界應變能釋放率的六分之一。本論文實驗結果可進一步與實際電子構裝結構受應力作用下之界面破壞力學參數配合，模擬互連系統界面脫層之成長。

Advanced microelectronic components typically consist of heterogeneous,multilayered layered interconnect structures made of metal conductor and ceramic or polymer based dielectrics. Dominant failure mode of these components is interface delamination induced by thermal or mechanical stresses. Predicting the reliability of these interconnect structure is challenging due to that the materials and associated processes are new and the responses of materials interfaces to stressing are unknown. Approach
presently used in the semiconductor and microelectronics industries for characterizing interconnect reliability is through either component- or system-level accelerated tests.Issues associated with this approach are that the cost is very high and the time needed is too lengthy for required technology development cycle time. Consequently, a
phenomenological model that could describe the ruptures of materials interfaces is desired for predicting reliability of interconnects. The desired modeling approach would
include analysis of driving forces for interfacial delamination, characterization of fracture toughness for the interface of interest and predicting the delamination growth. Focus of this study is on the characterization of interfacial fracture toughness.
In this research the critical strain energy release rate is obtained by using double cantilever beam fracture experiment. The experiment is conducted on a custom-developed micro tester. Interfaces considered are polyimide to silicon nitride thin film interface, polyimide to silicon substrate interface and polyimide to gold thin film interface. These interfaces are some of the common interfaces in state-of-the-art microelectronic packages. From the experimental results it is observed that the critical strain energy release rate for the interface of polyimide-silicon nitride is about three times
of that for the interface of polyimide-silicon. The higher toughness may be attributed to the higher roughness of the silicon nitride surface, which results in better mechanical
bonding to the polyimide thin film. It is also observed that the critical strain energy release rate for the interface of polyimide and gold is around one sixth of that for the interface of polyimide and silicon. Results of this study may be further combined with the fracture mechanics parameters determined for the interfaces in real electronic packages to predict the delamination growth in these structures.

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