國內半導體業經過了許多年的發展，相關的產業除了國內的競爭對手外，更面臨國際上的競爭；以封裝測試業來說，相關製程技術日趨成熟，以因應現今工業及民生電子產品的短、小、輕、薄的趨勢。近幾年，雖然台灣半導體薄膜覆晶封裝(Chip on Film, COF)技術已發展成熟，而液晶顯示器(Liquid Crystal Display，LCD) Driver IC之構裝(Assembly)為達成降低成本，並提升競爭力的需求，紛紛走向高腳數(High pin count)和細小間距(Fine Pitch)產品型態之設計；故高腳數與細小間距的產品為無法逆轉之唯一主流，造成封裝製程維持良率是一大考驗，各廠冀望在持續降低成本下，能夠維持產品良率穩定生產，如此才能有足夠的競爭力，生存於競爭激烈的國際市場中。
本研究的目的是應用田口方法，在薄膜覆晶壓合(Chip on Film；COF)封裝的內引脚壓合製程(Inner Lead Bonding Process；ILB)，探討在內引脚壓合時的相關參數設定，對於產品良率的影響。在案例製程中，研討出八個控制因子，包含一個二個水準的因子和七個三個水準的因子，接著應用田口方法的L18(21×37) 直交表列出十八種的參數組合，提出以不同壓合時間(Bonding Time)、壓合力量(Bonding Force)、不同的Tools及Stage尺寸、共平面度及材質作探討，實驗出各參數組合的ILB共平面度，以模擬分析獲得相關參數的最佳化設計。依據實驗後數據資料分析結果，經由田口方法得知，在過程中壓合壓力、時間等參數都會直接影響內引腳與凸塊接合後的良率。

The mainstream of the driver IC assembly is toward fine pitch and high‐pin count. The inner lead bonding (ILB) process is the most challenging part of chip on film (COF) manufacturing in view of its processing complexity. The purpose of this study is to explore the effect of co-planarity during Inner lead bonding process of chip on film assembly technology process by Taguchi experiment design.
This study is to identify the optimal parameters of bonding time and force by simulation analysis applying stress distribution of leads and bumps caused by various bonding time and force. According to the data analysis in Taguchi experiment design, it found out the parameters such as bonding force, bonding time and so on are to affect directly the yield rate of connecting leads and bumps.

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