本研究主要探討銅合金薄膜作為積體電路內連線系統材料之應用與分析。各種銅合金薄膜(銅(鈦)、銅(鉭)、銅(鋯))利用雙槍磁控濺鍍法製備，並將其沉積於二氧化矽/矽基材上。對於各種銅合金薄膜系統而言，本研究皆以兩種不同摻雜原子含量來討論。試片經500-800 oC真空退火後，吾人以歐傑能譜分析儀、拉賽福背向散射分析儀與X光光電子能譜儀分析摻雜原子與銅原子的擴散行為，並藉由θ-2θ X光繞射儀、低掠角X光繞射儀、掃瞄式電子顯微鏡與穿透式電子顯微鏡觀察薄膜的顯微結構。同時，使用四點探針量測各薄膜在室溫之片電阻值，並以該薄膜之厚度決定其電阻率。而薄膜與二氧化矽的附著性測試乃藉由Scotch tape test來評估。對於各薄膜的抗銅氧化性質而言，乃以薄膜片電阻的變化率及低掠角X光繞射儀來決定。此外，本研究亦以皮米安培計/直流電壓源來量測各不同電極MOS電容器之電流-電壓(I-V)曲線，並藉由此曲線判別各MOS電容器之漏電流大小。

　　實驗結果顯示，銅薄膜中之鈦、鉭、鋯等摻雜原子經退火後，會擴散至薄膜表面及薄膜與二氧化矽界面，並與氧原子反應而在表面與界面處形成一層額外氧化層。然而各摻雜原子在銅中的擴散行為並非一致，對於Cu(3.90 at.% Ti)與Cu(2.45 at.% Zr)薄膜而言，大多數的鈦、鋯等摻雜原子經700 oC退火後，會擴散至薄膜表面及薄膜與二氧化矽界面；然而Cu(2.28 at.% Ta)薄膜經700 oC退火後，大多數的鉭摻雜原子卻仍殘留在薄膜內。此外若與700 oC退火純銅薄膜相比，銅合金薄膜經700 oC退火後，銅原子擴散進入二氧化矽的程度較不嚴重，且銅合金薄膜與二氧化矽的附著性亦較佳。

　　電性量測結果顯示，當對MOS電容器施一外加電壓時，初鍍銅電極MOS電容器與初鍍Cu(0.03 at.% Ti)電極MOS電容器的漏電流都非常小(~10-8 A/cm2)。當各MOS電容器試片經700 oC退火後，純銅電極MOS電容器的漏電流顯著上升，然而Cu(0.03 at.% Ti)電極MOS電容器的漏電流卻仍非常小(~10-7 A/cm2)。由此漏電流之實驗結果可知，Cu(0.03 at.% Ti)電極MOS電容器的可靠度較佳。
對於試片的顯微結構而言，實驗結果顯示退火銅合金薄膜之表面型態優於純銅薄膜之表面型態。而隨著摻雜原子在銅中的含量增加，退火銅合金薄膜的孔洞成長程度與晶粒成長程度亦隨之降低。在各退火銅合金薄膜中，又以Cu(2.28 at.% Ta)薄膜表面所呈現的孔洞尺寸與晶粒尺寸為最小。然而就Cu(111)織構性質而言，卻是Cu(3.90 at.% Ti)系統與Cu(2.45 at.% Zr)系統展現較高程度的Cu(111)織構。

　　對於薄膜的抗銅氧化性而言，若銅合金薄膜先作700 oC的真空預熱處理，此類型試片在200 oC之大氣氣氛下展現較佳的抗銅氧化性，而其中又以預熱處理之Cu(3.90 at.% Ti)與Cu(2.45 at.% Zr)薄膜的抗銅氧化性為最佳。而對於薄膜電阻率而言，實驗結果顯示各銅合金薄膜之電阻率皆高於純銅薄膜之電阻率。若銅合金薄膜經真空退火後，其電阻率將明顯下降，然而各退火銅合金薄膜之電阻率仍較純銅薄膜之電阻率高。本研究對於薄膜電阻率之改變、摻雜原子之析出行為與薄膜表面型態等各實驗結果之關連亦有深入的探討。

　In this study, the characteristics of Cu alloy thin films and their applications as the materials of interconnect in integrated circuits were explored. Thin films of pure Cu and Cu along with Ti, Ta, and Zr with two different concentrations were deposited on SiO2/Si by magnetic co-sputtering. After deposition, all films were subsequently annealed at 500-800 oC in vacuum. The dissociated behaviors of various Cu alloy films on SiO2 was explored by Auger electron spectroscopy (AES), Rutherford backscattering spectrometry (RBS) and X-ray photoelectron spectroscopy (XPS). The microstructural evolution between Cu and Cu alloy films were examined by θ-2θ X-ray diffraction (XRD), glancing incident angle X-ray diffraction (GIAXRD), scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Simultaneously, the resistivity of all films, before and after annealing in vacuum, was calculated from the sheet resistance measured at room-temperature with a four-point probe and the film thickness. The adhesion between various Cu alloy films and SiO2 was determined by the scotch tape test. In addition, after the oxidation test, Cu and Cu alloy films were analyzed by the normalized sheet resistance and GIAXRD. In addition, to understand the leakage current, the current-voltage (I-V) cureves of various MOS capacitors with different metal gates were measured by using picoammeter/dc voltage.

　The experimental result reveals that Ti, Ta and Zr additives in Cu would diffuse outward to the free surface and the Cu alloy/SiO2 interface, and react with O2 to form an additional oxide layer upon annealing. However, the dissociated behaviors of 700 oC annealed Cu(3.90 at.% Ti), Cu(2.28 at.% Ta) and Cu(2.45 at.% Zr) thin films are different. The Ti and Zr additives in Cu would mainly diffuse outward to the free surface and the Cu alloy/SiO2 interface. On the contrary, the majority of the Ta additives would remain within the Cu layer. In addition, compared to the annealed pure Cu films, all the Cu alloy films showed less diffusion of Cu into SiO2 when annealing at 700 oC. Furthermore, the adhesion between film and SiO2 is better in Cu alloy samples than in pure Cu ones.

　The current-voltage measurement using metal-oxide-semiconductor (MOS) capacitor structure reveals low leakage current (10-8 A/cm2) for capacitors with as-deposited Cu(0.03 at.% Ti) and pure Cu metal gates. However, after annealing at 700 °C in vacuum, leakage current of MOS capacitors using pure Cu gate exhibits a dramatic increase of leakage current, while leakage current of capacitors with Cu(0.03 at.% Ti) gate remains at ~10-7 A/cm2, indicating that the Cu(0.03 at.% Ti)/SiO2 system possesses a superior reliability to the Cu/SiO2 system.

　The microstructural result shows that the surface morphology of Cu alloy films is superior to pure Cu films after annealing. The extent of void and grain growth decreases as the additives increases. Among all annealed Cu alloy films, the annealed Cu(2.28 at.% Ta) film shows the lowest degree of void and grain growth, but Cu(3.90 at.% Ti) and Cu(2.45 at.% Zr) films present higher degree of Cu(111) texture.

　According to the results of the oxidation test, the Cu alloy films pre-annealed at 700 °C reveal a superior oxidation resistance when annealed at 200 °C in air, especially for the pre-annelaed Cu(3.90 at.% Ti) and Cu(2.45 at.% Zr) films. In addition, the room-temperature resistivity of various Cu alloy films is higher than that of pure Cu films, but decreases as the annealing temperature increases. However, the room-temperature resistivity of all annealed Cu alloy films is still larger than that of pure Cu films with the same treatment. The relations between the resistivity variation and segregation of additives/surface morphology are also discussed.

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