行動手持裝置的興起，特別是智慧型手機與平板電腦己經成為半導體產業往高效能、高度功能整合與微型化及低功率發展的主要趨動力，此一趨勢也促使半導體封裝技術往三維立體方向發展。目前實務上有多種方式可將晶片做垂直堆疊整合，例如打線或覆晶加打線等混合技術。但隨著晶片間互連密度持續增加，互連間距的持續微縮，傳統的堆曡式封裝正面臨瓶頸。近年來運用直通矽晶穿孔(Through Silicon Via)的矽中介層(Silicon Interposer)連接術逐漸引起業界注目，因為它提供高佈線密度，容許極度微縮的互連間距，並因互連路徑的大幅縮短而享有較佳之電器特性。

隨著三維封裝技術(3D Packaging)的發展，伴隨而來的品質與成本問題成為產品能否大量進入商業化的重要因素，因此確保製程中矽中介層晶圓的良率事關重大。傳統上，測試與其衍生之費用是在整個封裝製程完成後才發生，但隨著矽中介層技術導入封裝製造，在製程中加入矽中介層測試以提高產品良率變得無可避免，相關測試成本也隨之而來。因此，如何降低由此衍生的測試成本為本文之主要研究目的。在本文中二種分別應用電容式與電阻式的測試方法，首先被提出來並探討其成本與產量的缺點，接著提出一種基於菊花鏈式之三明治結構的測試方法與前述二種方式進行比較，並詳述新方法在產量與測試成本的顯著改善之處。

Handheld devices, especially smart phones and tablet PCs, are driving the semiconductor industry to deliver more computing power and product features with smaller form factor and less energy consumption for compelling user experiences. The demand for high performance, low power, miniaturization and function integration has led to 3D (three dimensional) semiconductor packaging technologies. There are typical ways to stack IC chips in a vertical manner such as wire bonding or flip chip combining wire bonding technologies. However, as the interconnect density continues to increase and the interconnect pitch to shrink, conventional stack packaging has been facing bottleneck. In recent years, silicon interposer with TSV (through silicon via) interconnect technology has gained increasing attention. It provides higher routing density and much finer pitch with better electrical performance due to its shorter interconnect path.
Along with the development of interposer based packaging technologies, the quality and cost of the technology are critical for product commercialization, hence to ensure the quality of interposer in the manufacturing process has become crucial. Test cost is typically concerned at final test after assembly process is completed. With the introduction of silicon interposer for 3D package manufacturing, cost for extra in-process test to guarantee interposer quality before following bonding process can never be ignored. The major goal of this thesis is to find an effective test approach to minimize the cost implicated in the process. Two methods by capacitive and resistive approaches are discussed first to discover the issues on throughput and cost. A novel approach by a daisy chain structure is described and compared with the other two approaches. Significant throughput and cost per unit improvement are achieved by the novel approach.

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