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研究生: 簡尊彝
Chien, Tsun-I
論文名稱: 以渾沌為基礎之數位通訊系統之設計與分析
Design and Analysis of Chaos-based Digital Communication Systems
指導教授: 廖德祿
Liao, Teh-Lu
學位類別: 博士
Doctor
系所名稱: 工學院 - 工程科學系
Department of Engineering Science
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 83
中文關鍵詞: 混沌同步二進位相位調變I-CDPK非線性觀測器差動混沌調變混沌差動峰值調變混沌調變混沌安全數位通訊系統分插式混沌差動峰值調變BPSK混沌加解密分頻多工存取TDMA分時多工存取CDMAFDMA數位通訊系統分碼多工存取混沌多工存取DCSK
外文關鍵詞: TDMA, Chaotic synchronization, Nonlinear observer, Cryptography, Interleaved Chaotic Differential Peaks Keying mo, I-CDPK, BPSK, DCSK, Digital communication systems, Chaotic Multiple Access, Code Division Multiple Access, CDMA, Frequency Division Multiple Access, FDMA, Time Division Multiple Access, Secure chaotic digital communication systems, Chaotic modulation, Chaotic Differential Peaks Keying
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  • 本論文提出了三個以混沌調變、混沌加密、混沌同步及混沌多工存取為基礎的混沌數位通訊系統。在第一個所提出的混沌安全數位通訊系統中包含了混沌調變器(CM)、混沌安全傳輸器(CST)、混沌安全接收器(CSR)和混沌解調器 ( CDM )等四個主要的模組,其中CM是結合了一個混沌系統及一個新的混沌差動峰值調變(CDPK)技術來產生對應於輸入數位位元的類比混沌參數,而CST模組則用於傳送單一加密的混沌訊號送到公眾通道再由CSR接收,透過適當的非線性觀測器設計在CST及CSR中的混沌電路即能達到同步。另外在CST及CSR中各有一個子系統來作為產生加密鑰匙訊號及解密鑰匙之用,在CDM模組中設計了一個非線性觀測器來估測CM傳送過來的訊號再利用所提出的混沌差動峰值調變(CDPK)技術來解出傳送的數位資料,而在本文中也分別在時域及頻域上探討了此系統的安全性。第二個所提出的是一個應用分插式混沌差動峰值調變(I-CDPK)技術的無相關器式的數位通訊系統,而這個系統係由分插式混沌差動峰值調變器(ICM)、頻率調變(FM)發射器、頻率調變(FM)接收器及分插式混沌差動峰值解調器(ICDM)等四個模組所構成,在ICM模組中具有一個用來產生混沌訊號的混沌電路、用來做數位類比訊號轉換的數位/類比轉換器以及負責所有訊號及動作流程的數位控制機制藉以完成分插式混沌差動峰值調變,就I-CDPK技術而言,每一個混沌系統的狀態皆被用來傳送數位資料,透過適當的觀測器設計能使在ICM及ICDM中的混沌電路獲致同步而仍然只需由ICM傳送單一實數訊號至FM 發射器再由ICDM從(FM)接收器收到此單一實數訊號,經位元偵測器(Bit Detector)解調即可正確接收數位資料。另外,在本文中亦分析了此系統的位元錯誤率並與常見的二進位相位調變(BPSK)及以所提出的差動混沌調變(DCSK)做比較。第三個所提出的系統係以前述分插式混沌差動峰值調變(I-CDPK)技術為基礎的多工存取混沌數位通訊系統,與目前常見的多工存取技術相比,最大的不同為每一個傳送接收連結皆被分別指定到一個混沌系統狀態,使的這些連結可同時同頻率段傳輸資料,不需像分碼多工(CDMA)使用的二進位亂數碼,也不需像分時多工(TDMA)以不同的時間槽來區分不同的連結,亦不需像分頻多工(FDMA)將每個連結以不同的頻率段來傳輸,而且,本文亦藉由分別模擬三個相對的範例系統,來證明這三個系統於理論上的有效性。

    This dissertation presents three chaotic digital communication systems based on chaotic modulations, cryptography, chaotic synchronization techniques and chaotic multiple access. The first one is a secure chaotic digital communication system consisting of a Chaotic Modulator (CM), a Chaotic Secure Transmitter (CST), a Chaotic Secure Receiver (CSR) and a Chaotic Demodulator (CDM). The CM module incorporates a chaotic system and a novel Chaotic Differential Peaks Keying (CDPK) modulation scheme to generate analog patterns corresponding to the input digital bits. The CST and CSR modules are designed such that a single scalar signal is transmitted in the public channel. Furthermore, by giving certain structural conditions of a particular class of chaotic system, the CST and the nonlinear observer-based CSR with an appropriate observer gain are constructed to synchronize with each other. These two slave systems are driven simultaneously by the transmitted signal and are designed to synchronize and generate appropriate cryptography keys for encryption and decryption purposes. In the CDM module, a nonlinear observer is designed to estimate the chaotic modulating system in the CM. A demodulation mechanism is then applied to decode the transmitted input digital bits. Moreover, the security features of this proposed system in the event of attack by an intruder in either the time domain or the frequency domain are discussed. The second one is a novel non-correlator based digital communication system with the application of interleaved Chaotic Differential Peaks Keying (I-CDPK) modulation technique, which consists of four major modules: I-CDPK Modulator (ICM), Frequency modulation (FM) transmitter, FM receiver and I-CDPK Demodulator (ICDM). In the ICM module, there are four components: a chaotic circuit to generate the chaotic signals, A/D converter, D/A converter and a digital processing mechanism to control all signal flows and performs I-CDPK modulation corresponding to the input digital bits. For interleaving every input digital bit set, every state of the chaotic system is used to represent one portion of it, but only a scalar state variable (i.e. the system output) is sent to the ICDM’s chaotic circuit through both FM transmitter and FM receiver. An observer-based chaotic synchronization scheme is designed to synchronize the chaotic circuits of the ICM and ICDM. Meanwhile, the Bit Detector in ICDM is devoted to recover the transmitted input digital bits. The performance of bit error rate of the second system is analyzed and compared with those of the correlator-based communication systems adopting coherent Binary Phase Shift Keying (BPSK) and coherent Differential Chaotic Shift Keying (DCSK) schemes. The third one is a novel Chaotic Multiple Access Digital Communication system. In comparison with the current multiple access schemes, the key difference is that every link is assigned to a different state of the chaotic system. By using the proposed scheme, the transmission between all the three links can be achieved on the same frequency band at the same time without the need of the codes used in Code division Multiple Access (CDMA), different frequency bands for different transmitter/receiver pairs in Frequency Division Multiple Access (FDMA) and the separated time slots for all the links in Time Division Multiple Access (TDMA). Furthermore, some numerical simulations of three illustrative communication systems are given to demonstrate the theoretical effectiveness of these three proposed systems.

    Tables of Contents English Abstract…………………………………………III Chinese Abstract …………………………………………VI Acknowledgment ………………………………………VIII Tables of Contents ……………………………………IX List of Tables …………………………………………………………………………XII List of Figures ………………………………………………………………………XIII Chapter 1 Introduction …………………………………………………………………1 1.1 Chaos-based Communications …………………………………………………………1 1.2 Secure Chaotic Communications ……………………………………………………3 1.3 Chaotic Modulation Schemes …………………………………………………………5 1.4 Chaos-based Multiple Access ………………………………………………………6 1.5 New Chaotic Digital Communication Systems ……………………………………7 1.6 Organizations of this Dissertation ………………………………………………7 Chapter 2 Design of Secure Chaotic Digital Communication systems ……………9 2.1 Architecture of the Secure Chaotic Digital Communication System ………9 2.2 Design of Chaotic Modulator (CM): CDPK Scheme…………………………………11 2.3 Design of CST and CSR via Nonlinear Observer and Chaotic Cryptography ……………………………………………………………………………14 2.3.1 Nonlinear Observer …………………………………………………………………14 2.3.2 Design of CST and CSR ……………………………………………………………16 2.3.3 Chaotic Cryptography ………………………………………………………………17 2.4 Design of CDPK Demodulator (CDM) …………………………………………………18 Chapter 3 Illustrative Secure Chaotic Digital Communication System, Simulations and Security Analysis …………………………………………………………20 3.1 An illustrative Secure Chaotic Digital Communication System ……………20 3.2 Simulation Results ……………………………………………………………………25 3.3 Discussions on Security ……………………………………………………………29 Chapter 4 Non-Correlator-based Chaotic Digital Communication System: I-CDPK Scheme …………………………………………………………………………………34 4.1 Architecture of the Non-Correlator-based Chaotic Digital Communication System …………………………………………………………34 4.2 I-CDPK Modulator (ICM) …………………………………………………………36 4.3 I-CDPK Demodulator (ICDM) …………………………………………………………40 4.4 Observer-based Chaotic Synchronization …………………………………………41 Chapter 5 Performance Analysis of the Chaotic Digital Communication System: I-CDPK Scheme …………………………………………………………………43 5.1 An illustrative Communication System ……………………………………………43 5.2 Simulation Results ……………………………………………………………………45 5.2.1 Simulation Results for Situation 1 ……………………………………………45 5.2.2 Simulation Results for Situation 2 ……………………………………………47 5.3 Bit Error Rate Analysis ……………………………………………………………49 5.4 Hardware Implementation ……………………………………………………………54 Chapter 6 Multiple-Accessing Chaotic Digital Communication System: I-CDPK Scheme …………………………………………………………………………………………55 6.1 Architecture of the Multiple-Accessing Chaotic Digital Communication System ………………………………………………………………………55 6.2 Multiple Access using I-CDPK Scheme ……………………………………………57 6.3 Multiple-Accessing Chaotic Transmitter ………………………………………59 6.4 Multiple-Accessing Chaotic Receiver ………………………………………………61 6.5 Simulation Results and Bit Error Rate Performance …………………………65 6.5.1 Simulation Results …………………………………………………………………65 6.5.2 Bit Error Rate Performance ………………………………………………………69 6.6 Extension to Total Links ……………………………………………………………70 Chapter 7 Conclusions and Remarks on Future Research …………………………72 7.1 A Summary of this Dissertation ………………………………………………72 7.2 Perspective of Future Research ……………………………………………………74 Reference …………………………………………………………………………………76 Curriculum Vitae ……………………………………………………………………………83

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