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研究生： 張幃傑
Chang, Wei-Chieh
論文名稱： 低溫下對於超薄基體埋入氧化層全空乏絕緣上覆矽金屬氧化物半導體場效電晶體之介面缺陷分析與模擬
Analysis and Modeling of Interface Traps for Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperatures
指導教授： 江孟學
Chiang, Meng-Hsueh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年： 2024
畢業學年度： 112
語文別： 英文
論文頁數： 106
中文關鍵詞： 低溫 、陷阱 、介面電荷 、曲折 、帶尾 、次臨界擺幅(SS) 、超薄基體埋入氧化層全空乏絕緣上覆矽(UTBB-FD-SOI) 、科技電腦輔助設計(TCAD)
外文關鍵詞： cryogenic temperature, trap, interface charge, inflection, band tail, subthreshold swing (SS), UTBB-FD-SOI, TCAD
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    • 本篇論文藉由科技電腦輔助設計(TCAD)模擬探討在低溫操作下半導體的特性(如遷移率、次臨界擺幅(SS)，以及帶尾)，並著重分析電晶體的轉移特性所發生的曲折(Inflection)現象。曲折現象源自於介面缺陷能態捕捉載子，進而產生介面電荷，由於此現象隨著溫度的下降，其在電晶體元件電性的影響越發明顯，因此本研究近一步分析缺陷的濃度大小、分佈範圍與位置對電性所產生的影響，以此條件去比較不同操作溫度下的差異。
    最後模擬超薄基體埋入氧化層全空乏絕緣上覆矽(UTBB-FD-SOI)架構 MOSFET元件，分析於低溫操作環境，不同埋入氧化層厚度與後閘極偏壓之下曲折的趨勢變化，藉由調變後閘極(back gate)偏壓減緩介面陷阱所導致的電性退化。

    This thesis investigates the characteristics of semiconductors under cryogenic temperature operation through Technology Computer Aided Design (TCAD) simulations (such as mobility, subthreshold swing (SS), and band tail). We particularly focus on analyzing the Inflection phenomenon occurring in the transfer characteristics of transistors. The Inflection phenomenon originates from the trapping of carriers by interface trap states, resulting in the generation of interface charges. As this phenomenon becomes more pronounced with the decrease in temperature, its impact on the electrical characteristics of the transistor becomes increasingly significant. This thesis further analyzes the influence of trap concentration, distribution range, and location on the electrical characteristics. It compares the variations at different temperatures based on these conditions.
    Finally, we simulate MOSFET devices with Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB-FD-SOI) architecture. Analyzing the trends of Inflection under different buried oxide thicknesses and back gate biases at cryogenic temperature.

    摘要 I Abstract III 誌謝 IV Table Captions VIII Figure Captions IX Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 2 1.3 The Framework of the Thesis 3 Chapter 2 TCAD Calibration of 40-nm Bulk nMOSFET 4 2.1 Design Rules of nMOSFETs 4 2.2 The Basic Physical Model Used for Simulation 7 2.2.1 Fermi and Temperature Model 7 2.2.2 Effective Intrinsic Density Model 7 2.2.3 Recombination Model 8 2.2.4 Philips Unified Mobility Model 8 2.3 The Physical Models Used for Calibration 9 2.3.1 Lombardi Mobility Model 9 2.3.2 High Field Saturation Mobility Model 11 2.3.3 Traps Model 12 2.4 Calibration Methodology 14 2.4.1 Calibration Introduction 14 2.4.2 ID-VG Calibration (Low Drain Bias Voltage) 15 2.4.3 ID-VG Calibration (High Drain Bias Voltage) 17 2.4.4 ID-VD Calibration 19 Chapter 3 Characteristics of Semiconductor at Cryogenic Temperature 20 3.1 Mobility 20 3.2 Subthreshold Swing 23 3.3 Band Tails 24 Chapter 4 Analysis of the Phenomenon of Traps on Electrical Characteristics in Cryogenic nMOSFETs 30 4.1 Interface Charge 30 4.1.1 Traps Distribution 30 4.1.2 Level State Distribution of Traps 32 4.1.3 Gaussian State Distribution of Traps 36 4.1.4 The Impact of Gaussian State Distribution Variations 43 4.2 The Problem of Subthreshold Swing Distortion in the Gaussian State Caused by TCAD Calculation. 52 4.3 Fixed Charge 54 Chapter 5 Performance of the UTBB FD-SOI MOSFETs Affected by Inflection at Cryogenic Temperatures 57 5.1 Overview of UTBB FD-SOI 57 5.2 Design Rules of UTBB FD-SOI nMOSFETs 61 5.3 Analyzing Inflection Behavior in UTBB FD-SOI nMOSFETs at Cryogenic Temperatures by Back Gate Voltage Adjustment. 64 Chapter 6 Conclusion 86 References 88

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