為了克服元件微縮過程中遇到的諸多問題，多晶矽閘極與二氧化矽介電層需以金屬閘極與高介電常數材料取代之。本研究主要探討HfOx-TiOx介電薄膜疊層的材料性質與電性表現之間的關係，並配合純HfOx、純TiOx為對照組，藉以評估其作為積體電路閘極介電層之可行性。
HfOx-TiOx疊層介電薄膜以磁控濺鍍法製作於矽基板上，經過300℃退火，並搭配W為金屬閘極形成MOS (Metal-Oxide-Semiconductor) 結構電容器。MOS電容器的電容—電壓 (C-V) 曲線以阻抗分析儀在100 kHz及1 MHz兩種頻率下進行量測，之後再進行修正；電流—電壓 (I-V) 曲線則以半導體參數分析儀量得。材料分析方面，使用高解析穿透式電子顯微鏡觀察薄膜截面影像，判斷薄膜厚度與其微結構。另以X光光電子能量分析儀被用來進行介電層薄膜及矽基板間的化學鍵結狀態分析，藉以觀察薄膜的電性表現、材料性質隨著疊層變換的情況。
C-V量測果顯示，初鍍的試片雖然等效二氧化矽厚度 (EOT) 小於2 nm，但I-V量測顯示其漏電流過大。經300℃退火後，TiOx/HfOx、HfOx/TiOx的MOS疊層電容器的EOT值均略微增大，但TiOx/HfOx的MOS疊層電容器之漏電流值比相同EOT之二氧化矽介電層的漏電流密度還要小6個級數，而比相同EOT之HfO2介電層的漏電流密度小1~2級數。
藉由XPS分析結果，可知薄膜在初鍍時，Hf及Ti之化學鍵結已呈現氧化態，300℃退火後，其鍵結狀態沒有太大的改變。從HRTEM影像，發現無論退火前後，所有試片皆有中介層產生於介電層與Si基材的界面之間，且所有介電層薄膜是非晶質結構。此外，退火後的HfOx/TiOx、TiOx/HfOx的MOS疊層電容器之介電層已經混合而形成HfTiOx一層介電氧化層。

Device in integrated circuits are continuously shrunk to reach higher device density, faster operation speed and lower power consumption. However, many problems are encountered while scaling. To overcome those problems, the poly-Si gate electrode and SiO2 dielectric should be replaced by metal gate electrodes and high-k dielectrics. In this study, we investigate the electrical and material properties of alternative stacking of HfOx -TiOx (HfOx/TiOx and TiOx/HfOx) dielectric films, and compare their performance with pure HfOx and pure TiOx dielectric films.
Alternative stacking of HfOx and TiOx dielectric thin films were deposited on Si substrates by sputtering from Hf and Ti targets, respectively. Post-deposition annealing at 300℃ was performed to eliminate the defects within the dielectrics or at the interface. The dielectric layers were covered with a W electrode to form metal-oxide-semiconductor (MOS) capacitors. MOS capacitors with various stacked dielectrics were studied electrically using capacitance-voltage (C-V) and current–voltage (I-V) analysis. The thicknesses of films were determined by high-resolution transmission electron microscopy (HRTEM), and the microstructure was also characterized. X-ray photoelectron spectroscopy (XPS) was applied for chemical bonding analysis between dielectric films and Si substrate.
The C-V curves are measured at two frequencies (100 kHz and 1 MHz) under a designated equivalent circuit of capacitor and resistor in parallel. A modified C-V curve corresponding to the equivalent circuit with an additional serial resistor can be calculated from the two C-V curves measured at 100 kHz and 1 MHz. EOT was extracted from the accumulation capacitance of the modified C-V curves. All as-deposited dielectric layers possess an EOT of less than 2 nm. However, the leakage current of this sample is too large to be practical.
After annealing, the EOT values of both HfOx/TiOx and TiOx/HfOx increase slightly. However, in comparison with the SiO2 benchmark line and HfO2 benchmark line, the leakage current densities of annealed TiOx/HfOx dielectric could be lowered by 6 orders and 1~2 orders, respectively. From HRTEM images, an interfacial layer still forms at the interface between the high-k dielectrics and Si substrate and the dielectric films are amorphous. Additionally, the bilayer dielectric (HfOx/TiOx and TiOx/HfOx) actually had mixed together after annealing. From the XPS spectra, the as-deposited dielectric films had already been oxidized, and the annealed dielectric films have similar chemical binding energy.

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