在本論文中，我們研究的主要目的集中在基於二維材料的元件製造與降低生產成本上。我們透過許多材料特徵技術，例如原子力顯微鏡、掃描式電子顯微鏡、穿透式電子顯微鏡、拉曼光譜儀和光激發光系統來研究材料品質和特性。
首先，我們嘗試透過使用WSe2-MoS2異質水平結構來製作元件。其電流與電壓特性顯示，在正向電壓時電流是低的，而反向電壓時電流卻是急劇增加的。這整流特性可以支持MoS2和WSe2之間存在水平n-p接面的特徵。然後，我們已經展示了利用單層的WSe2-MoS2水平接面作為導電之p-n通道的準異質接面雙極電晶體。從電性結果來看，在我們的二維準異質接面雙極電晶體中能實現的最大共射極電流增益約為3左右。有趣的是，我們還從電性量測中觀察到負微分電阻特性。我們認為引起負微分電阻特性是由於在基極區和集極區中施加高電壓時形成量子井而造成共振穿隧現象。
此外，我們還展示了採用MoS2材料的場效電晶體，該電晶體可在同一元件中選擇性操作p型或n型特性。且該元件具有可調整的臨界電壓（Vth），可以透過添加一層等離子化的介電層在上閘極結構上來改變該臨界電壓。由於成長相對較薄的介電層促進了氧的過量，這使得在該介電層中產生負電荷，而不是在底部介電層中常見的正電荷。因此，造成臨界電壓位移並且上閘極結構特性從典型的n型切換到p型，而在施加下閘極電壓時仍保持n型行為。通過施加上閘極脈衝，甚至可以進一步微調元件臨界電壓的特性。因此，這已經證明了具有可調整元件特性的互補邏輯反相器。與現有研究相比，我們的元件可以節省幾乎兩倍單個元件的處理時間和價格。這個概念對於未來製造先進元件是非常有用和有價值的。
未來準異質接面雙極電晶體可通過減少基極區寬度及摻雜射極，可以大大改善電流增益過小和電流密度過小的問題。我們還將提供有效的隔離機制，以防止電壓信號混合進入我們的雙閘極元件。然後，為了獲得理想的轉換電壓並確保反向器完全電壓匹配，在將來的設計中，兩個器件（p型和n型）的尺寸應相同。我們相信這些發現對於新型電子產品的未來發展將是引人入勝的。

In this thesis, the main purpose of our research is focused on the fabrication of the 2D-material based devices and lower the cost of production. Plenty of material characterization techniques such as atomic force microscopy、scanning electron microscope、transmission electron microscopy、raman spectrometer and photoluminescence system have been used to study the quality and characteristics.
First, we tried to fabricate the device by using the lateral WSe2-MoS2 heterostructure. The current-voltage characteristics exhibits that current is low in the forward bias whereas current is abruptly increase in the reverse bias. This rectifying characteristic is displayed to support lateral n-p junction formation between MoS2 and WSe2. Then, we have demonstrated the quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel. From the result of electrical characteristics, the maximum common-emitter current gain achieved is around 3 in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. We think that the NDR behavior is caused by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages in the base region and collector region.
Furthermore, we also have exhibited the MoS2–based field effect transistor with the selective operation of either p-type or n-type characteristic in the same device. The device is built with an adjustable threshold voltage (Vth), which can be varied by adding a layer of plasma-oxidized dielectric at the top gate structure. This facilitates a surplus of oxygen due to the relatively thin grown dielectric layer and creation of negative charges in that layer instead of the usual ones of positive polarization in the bottom dielectric layer. Consequently, the Vth shifts and the top gate structure switch from the typical n-type to p-type while n-type behaviour remains in the application of bottom-gate voltages. And the Vth for device characteristics can be slightly adjusted further by applying a gate pulse input. Accordingly, the complementary logic inverters with the adjustable device characteristics have been demonstrated. Compared to the existing research, our device could save almost twice the process time and price of an individual device. This concept is useful and valuable for the future fabrication of advanced devices.
In the future, we can be greatly improved the problems of the small current gain and small current density by reducing the base region and doping the emitter region for the quasi-heterojunction bipolar transistor. And we will also give the effective isolation mechanism to prevent bias signals from mixing for our dual gate device. Then, in order to get the ideal switching voltage and ensure the inverter fully voltage matched, the dimension for two devices (p-type and n-type) should be the same in the future design. We believe that these discoveries will be fascinating and promising for the future development of new type electronics.

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