近年來離散小波轉換(Discrete Wavelet Transform)在多重解析度分析(Multiresolution Analysis)和數位影像處理(Digital Image Processing)方面有非常廣泛的應用，相較於FFT、DCT等方法，小波轉換具有較高的壓縮率以及自我相似特性的資料結構。例如近年來所盛行的JPEG2000壓縮格式也是建構在離散小波轉換的基礎上。而在各種的離散小波轉換理論中，Daubechies離散小波轉換是正交且具有較佳的連續特性的方法之一，利用一維的Daubechies小波轉換，分別對影像的行與列資料做處理，藉以完成一個二維的小波轉換。此架構是以遞迴金字塔演算法的概念為基礎，配合Daubechies小波轉換的高、低頻率波係數來達成。研究的主要目的是以硬體架構來實現尺寸函數(scaling function)與母小波函數(mother wavelet function)。為了降低硬體在實現小數運算的誤差，設計以20位元的定點(fixed-point)運算的技術來近似浮點(float-point)運算。此外，為了降低FPGA內部空間地浪費，採用具有10MHz速度的 SRAM來存取資料，以達到更有效率的FPGA容量應用。最後以一灰階型態BMP檔案來做影像壓縮的處理，並可以成功的得到原來資料量一半的BMP圖檔，如此可以減低儲存空間的使用。在本論文中，是以硬體描述語言(VerilogHDL)來描述Daubechies小波轉換，再利用Xilinx SPARTAN-IIE XSC300e FPGA來驗證。

　　In recent years, the discrete wavelet transform is widely application on multi-resolution and digital image processing. To compare with FFT, DCT methods etc., the wavelet transform has high compression-ration and self-similarity property data structure. For example, the popular compression format of JPEG2000 is based on the discrete wavelet transform. For different kind discrete wavelet transform theorems, Daubechies has better continuous property and known orthonormal wavelet. Using one dimension Daubechies wavelet transform to process the row and column data of image respectively, this method can accomplish two dimension wavelet transform. This structure is based on a concept of pyramid algorithm and archived it by design high-pass and low-pass filters of Daubechies. The purpose of this research is using hardware structure to implement the scaling functions and mother wavelet functions. In order to reduce the error of decimal calculation, we design the 20 bits fixed-point calculation technique to approximate the float-point calculation. In order to reduce the FPGA internal space waste, we used the extra SRAM to access the data. In verification, we used a gray level, BMP format image to compress. After compressing, the image data size is a half of the original image data; it can reduce the utility of memory space. In this theory, we design the Daubechies wavelet transform by VerilogHDL, and verify it on Xilinx SPARTAN-IIE XSC300e FPGA.

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