Graphene, a two-dimensional sheet of carbon atoms, has many extraordinary physical, chemical and electronic properties, and is thus of great interest in many scientific and engineering fields. However, before graphene can be applied at the mass-production scale, there are many practical problems to be overcome. This thesis considers three particular issues involved in the application of graphene to next-generation electronics. The thesis commences by investigating the feasibility of using tri-layer graphene films as a diffusion barrier for the Cu interconnects in integrated circuit (IC) devices. The microstructural, electrical and mechanical properties of graphene on flexible polyimide (PI) substrates under cyclic loading are then examined in order to evaluate the potential of graphene for flexible electrode applications. Finally, a novel method to synthesis large-area graphene for mass-production is proposed.
Modern semiconductor chips are characterized by an ever-increasing number of metallization layers and IC density. Thus, thin diffusion barriers are required in order to minimize the volume ratio of the diffusion barrier to the conducting line. No reliable barrier currently exist for Cu interconnects with a thickness of less than 3 nm or which meet the line resistance scaling requirements specified by the International Technology Roadmap for Semiconductors (ITRS). However, this thesis presents the thinnest ever reported Cu diffusion barrier in the form of a 1-nm-thick graphene tri-layer. The X-ray diffraction patterns and Raman analysis results show that the graphene film remains thermally stable up to temperatures as high as 750°C. Moreover, the transmission electron microscopy results show that no inter-diffusion occurs in the Cu/graphene/Si structure. However, the Raman analyses show that the graphene degrades to a nanocrystalline structure at temperatures higher than 750°C. For example, at 800°C, the perfect carbon structure of graphene is damaged, and thus the ability of graphene to function as a Cu diffusion barrier is seriously impaired.
Preliminary research has suggested that graphene has significant potential for the realization of flexible electronics. However, the literature lacks a detailed examination of the electrical resistance and structural properties of graphene on flexible substrates. Thus, this thesis prepares three kind of multi-layer graphene/polyimide (PI) specimens with three, six and nine graphene layers, respectively. A self-designed bending tester is then used to investigate the electrical properties of the specimens under various bending cycles and bending frequencies. The investigations focus specifically on the electrical resistance of the specimens during bending and the rate of increase of the electrical resistance with the number of bending cycles and bending frequency as a function of the total graphene thickness. The results reveal that the voids formed at the interface between adjacent layers in the graphene/PI specimens during the transfer preparation process increase in size with an increasing number of bending cycles and lead to a disconnection between the graphene layers and the PI substrates. Moreover, the electrical resistance increases with a reducing graphene thickness and an increasing number of bending cycles. For a given graphene thickness, the Raman peak intensity ratio ID/IG value increases exponentially with an increasing number of bending cycles or an increasing bending frequency. In addition, a higher value of ID/IG is accompanied by both a higher rate of increase of the electrical resistance and a higher L1/L2 aspect ratio (where L1 and L2 are the half lengths of the long and short axes, respectively, of the selected-area electron diffraction pattern of graphene). Finally, the tilt angle of the upper layer of graphene in the specimens increases with an increasing graphene thickness for a given bending frequency. Furthermore, for a given graphene thickness, the tilt angle increases as the bending frequency increases.
Various methods are available for the growth of large-area, high-quality graphene on the surfaces of metal catalysts using chemical vapor deposition (CVD) techniques or solid carbon sources. However, these methods require a nearly oxygen free environment which limits their use in mass production. This thesis demonstrates a non-vacuum (air annealing) process for the growth of high-quality graphene films on the surfaces of carbon-added polycrystalline nickel (Ni) film with the assistance of a SiO2 capping layer. Notably, it is shown that the number of graphene layers can be manipulated by controlling the amount of carbon embedded in the Ni film prior to annealing. The Raman analysis results, transmission electron microscopy observations, and electron diffraction patterns of the samples show that graphene films can be grown in air with an oxygen blocking layer and a 10 °C/s cooling rate in an open-vented rapid thermal annealing chamber or an open tube furnace. The quality of the air-annealing grown graphene is comparable to that of commercially available graphene grown using CVD. Notably, the proposed synthesis method is both simpler and cheaper than CVD methods, and is thus far better suited for mass production.

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