本篇論文主要透過有限元素模擬晶圓接合過程，找出影響晶圓準確接合的原因，並以實驗驗證。由於近年來，半導體、光電及通訊產業的蓬勃發展下，具有低電壓、高速度、低功率等優點的元件製作上都會使用到晶圓接合技術，而晶圓接合加工時所產生的應力和翹曲會影響到元件的特性，晶圓的準確接合對後段的封裝製程影響甚大，再加上大尺寸晶圓片讓晶圓接合的困難度及成本提高，所以研究中期望透過模擬的方式減少實驗成本支出找出影響晶圓準確接合的問題。
研究中將晶圓接合中產生偏移或是接合不良，歸因於晶圓前段製程和晶圓接合過程兩個問題來源。再從問題來源中找出製程前晶圓翹曲、機台的平整度、中心頂柱的作動方式等，利用有限元素模擬其接合過程，並與實驗結果比較。

In this study, finite element simulation is used to wafer bonding process, finding out the reasons to affect wafer bonding and accuracy, and verified. In recent years, semiconductor, optoelectronics and telecommunications industry, flourishing under the low-voltage, high speed, low power production on the advantages of the device will be used to wafer bonding technology, and wafer bonding process arising from the stress and warpage will influence the device characteristics, The accuracy of wafer bonding affects following packaging process deeply, and large-size wafer to wafer bonding increase difficulty and costs, the study hope that simulation to reduce costs to find affection of accuracy for wafer bonding problems..
In this study, the problem of wafer bonding offset or bonding worse, due to wafer manufacture and wafer bonding process. And then find out the wafer warpage, the flatness of the machine, the center pin actuation, the factors that may affect the accuracy of bonding, using the finite element simulation of the bonding process and comparison with experimental results.

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