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研究生: 王凱立
Wang, Kai-Li
論文名稱: 應用於軟體無線電射頻前端系統之低雜訊放大器與開關之研製
Design and Implementation of Low-Noise Amplifier and Switches for RF front-end system of Software Defined Radio
指導教授: 王永和
Wang, Yeong-Her
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 112
中文關鍵詞: 砷化鎵低雜訊放大器收發機開關單石微波積體電路
外文關鍵詞: GaAs, LNA, T/R Switch, MMIC
相關次數: 點閱:116下載:16
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  • 軟體無線電在近年來由於無線通訊的蓬勃發展,能夠以編寫程式碼適應目前通訊協議的快速更迭,而具有相當彈性化的優勢,但其本身的線性度以及抑制雜訊的能力卻相當不足。本論文主要目的為設計一個射頻前端系統以解決軟體無線電本身動態範圍不足的問題,並且使得訊號能夠在天線與接收與發射端之間作路徑切換。
    本論文首先使用了穩懋0.15μm pHEMT 製程,實現K 頻帶低雜訊放大器,可以提升SDR 本身的動態範圍以及降低雜訊指數。本電路架構為二級的放大器,利用傳輸線作為阻抗匹配以增加佈局自由度,達到電路微小化的目的,並且在一二級中皆使用了源級退化做為降低雜訊的方式。量測結果本電路在19.2GHz 下有18.9dB 的增益,3dB 頻寬為4.8GHz,雜訊指數在20GHz 下有最佳值2.5dB,輸入1dB 功率壓縮點量測於19GHz,值為-12dBm,輸入三階截斷點量測於19GHz,通道間隔5MHz,值為-9.5dBm,核心晶片面積為1.33*0.667mm2。
    本論文第二部分則是利用穩懋0.15μm pHEMT 製程,製作使用於K 頻帶的單刀雙擲開關。本電路利用二極體作為開關元件,可以得到較高的訊號功率耐受度。量測結果本電路在20~25GHz 下其輸入損耗小於3dB。線性度方面,三階截斷點量測於23GHz,通道間隔為5MHz,其值為38dBm。整體晶片的核心面積為0.7*1.5mm2。
    第三部分利用穩懋0.15μm pHEMT 製程,設計一個雙頻段電晶體單刀雙擲開關,本開關利用四分之一波長傳輸線作匹配,並使用電晶體作為開關元件,可免除功率消耗。其中所匹配的頻段分別為K 及Ka 頻帶。量測結果得知模擬有誤,雙埠皆匹配在K 頻帶,輸入損耗自15~21.5GHz 皆小於2.5dB,隔離度皆大於23dB。線性度方面,輸入1dB 功率壓縮點量測於20GHz 有7dBm,三階截斷點量測於20GHz,通道間隔為5MHz,值為22dBm。晶片核心面積為0.65*1.7mm2。
    本文的最後一個電路為一個新型的雙刀雙擲開關,可使用在切換頻分雙工的SDR之訊號路徑。本電路利用FR4 印刷電路板製作,主頻為2.4GHz,以二級體作為開關元件。本論文中同時製作了四分之一波長雙刀雙擲開關與單刀雙擲開關做為比較使用。
    本電路的三級傳輸線架構能夠較二級架構有著更高的隔離度,並且本電路在將其中一端接上50 歐姆的電阻也可作為單刀雙擲開關使用。量測結果中,本架構的隔離度為30dB,大幅優於傳統雙刀雙擲開關的21dB 與單刀雙擲開關的16dB。

    The objective of this research is resolving the bad dynamic range and high noise figure of the SDR module. The additional LNA can help to lower the noise figure, while the SPDT and DPDT switch can change the signal route for TDD and FDD use, respectively. First, the K-band GaAs LNA uses source degeneration and resistor to improve overall noise figure and stability, GaAs process also gives high gain. The measured result shows 18.9dB highest gain at 19.2GHz and NF less than 3.1dB over Kband, while the circuit remains stability. Second, the K-band GaAs diode SPDT switch uses diode two control the signal path, by use this, the switch has high power durability.
    The measured result shows the insertion loss less than 3dB from 20 to 25GHz, and the highest linearity IIP3 reaches 38dBm. Third, the K-band GaAs Dual-band FET SPDT switch uses quarter-wavelength to matching the impedance, and the circuit consumes no power. The frequency is designed to K and Ka-band, while the measured result shows two ports are mismatched to K-band. The insertion loss less than 2.5dB from 15 to 21.5GHz, IIP3 and P1dB measured at 20GHz is 7 and 22dBm. Final, the MIC DPDT switch is a novel architecture, which has much more better isolation than quarterwavelength DPDT switch. The circuit is fabricated on FR4 board and the measured result show the highest isolation 30dB higher than the 21dB on quarter-wavelength DPDT and 16dB on SPDT switch.

    目錄 中文摘要 ........... I 英文摘要 ........... III 致謝 ........... VIII 目錄 ........... X 圖目錄 ........... XIV 表目錄 ........... XX 第一章 緒論......... 01 1.1 研究動機與背景........ 01 1.2 章節概述......... 03 1.3 參考文獻......... 04 第二章 射頻前端收發機架構與基本概念..... 05 2.1 收發機架構之簡介....... 05 2.2 基本參數......... 06 2.2.1 雜訊指數......... 06 2.2.2 轉換增益/損耗......... 08 2.2.3 穩定度.......... 08 2.2.4 動態範圍......... 09 2.2.5 三階交錯點........ 10 2.3 小結......... 12 2.4 參考文獻......... 13 第三章 K 頻段低雜訊放大器........ 14 3.1 相關研究發展現況....... 14 3.2 研究動機與架構簡介........ 14 3.3 K 頻段低雜訊放大器........ 16 3.3.1 電路設計......... 16 3.3.2 電路佈局圖........ 18 3.3.3 電路模擬與量測........ 19 3.3.3.1 模擬結果........ 19 3.3.3.2 量測儀器架設........ 23 3.3.3.3 量測結果與模擬比較....... 25 3.3.4 結果與討論........ 29 3.4 參考文獻......... 30 第四章 K 頻段二極體單刀雙擲開關....... 32 4.1 相關研究發展現況......... 32 4.2 研究動機與架構簡介........ 32 4.2.1 二極體模型........ 33 4.3 K 頻段二極體單刀雙擲開關....... 33 4.3.1 電路設計......... 33 4.3.2 電路佈局圖........ 35 4.3.3 電路模擬與量測........ 37 4.3.3.1 模擬結果........ 37 4.3.3.2 量測儀器架設........ 42 4.3.3.3 量測結果與模擬比較....... 44 4.3.4 結果與討論........ 48 4.4 參考文獻......... 50 第五章 K 與Ka-band 雙頻段電晶體單刀雙擲開關..... 52 5.1 相關研究發展現況......... 52 5.2 研究動機與架構簡介........ 52 5.2.1 四分之一波長傳輸線阻抗轉換...... 53 5.3 K 與Ka-band 雙頻段電晶體單刀雙擲開關..... 54 5.3.1 電路設計......... 54 5.3.2 電路佈局圖........ 56 5.3.3 電路模擬與量測........ 59 5.3.3.1 模擬結果........ 59 5.3.3.2 量測儀器架設........ 64 5.3.3.3 量測結果與模擬比較....... 65 5.3.4 結果與討論........ 70 5.4 參考文獻......... 77 第六章 一種新型的八分之一波長二極體雙刀雙擲開關... 79 6.1 相關研究發展現況......... 79 6.2 研究動機與架構簡介........ 80 6.2.1 HSMS-2860 二極體模型....... 81 6.3 新型八分之一波長二極體雙刀雙擲開關...... 85 6.3.1 電路設計......... 85 6.3.1.1 電壓最佳化......... 88 6.3.1.2 線寬最佳化......... 90 6.3.2 電路佈局圖........ 92 6.3.3 電路模擬與量測........ 95 6.3.3.1 模擬結果........ 95 6.3.3.2 量測儀器架設........ 100 6.3.3.3 量測結果與模擬比較....... 101 6.3.3.4 量測結果與四分之一波長雙刀雙擲、單刀雙擲開關比較.. 104 6.3.4 結果與討論........ 106 6.4 參考文獻......... 107 第七章 結論........... 108 7.1 結論........... 108 7.2 未來研究......... 109 7.2.1 雙頻段二極體單刀雙擲開關....... 109 7.2.2 應用於軟體無線電之射頻前端系統模組.... 111

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