本論文實現一個操作在ISM頻帶(Industrial Scientific Band), 可接收並解調振幅鍵控調變(OOK)的超低功耗喚醒接收器，本設計使用台積電提供的0.18微米CMOS製程。在喚醒接收機的架構方面，本篇論文實作了兩顆晶片，第一顆晶片是以包絡檢測器及作為喚醒接收機的第一級，由於這類架構雖然可以實現超低功耗，但整體的靈敏度受限於包絡檢測器，因此透過動態基極偏壓補償閥值電壓來提升檢測器的轉換增益，進而提升靈敏度，當中檢測器與後級電路透過交流耦合來區隔直流偏壓，考量到喚醒接收器屬於大部分的時間都不會有輸入訊號的運作機制，在等待喚醒碼進入的同時，可能會因為環境的干擾而造成誤判進而送出喚醒訊號，因此在比較器及相關器方面採用可調閥值的架構以抵抗環境的干擾，以利於成功產出喚醒訊號。目標喚醒碼以及比較器閥值皆由一個數位合成電路的SPI 所設定。第一顆晶片的電源電壓為0.6 V，功耗為10奈瓦，靈敏度為-67 dBm。
第二顆晶片是在第一顆晶片的基礎上更進一步的提升靈敏度，主要有兩項的修正，第一個是調整第一顆晶片中檢測器級數的選擇方式以及最優化電晶體工作區間電源電壓也因此調整到1 V，來提升匹配電路的被動增益並最佳化檢測器輸出的訊雜比，第二個修正中，由於第一顆晶片裡的利用交流耦合電容實現上會有一些缺點，因為交流耦合電容與後級的輸入阻抗會形成高通效應，而檢測器的輸出在頻譜上落於直流低頻區，因此耦合電容值要夠大才能避免檢測器的輸出被衰減，而當容值夠大又會影響系統的安定時間，限制了資料傳輸速率，因此利用一個共模回授電路來建立系統間的直流偏壓取代掉原本的交流耦合電容，後級採用與第一顆晶片相同的比較器及相關器，最後整體功耗在輸入電源1 V時，功耗40奈瓦，靈敏度 -81.5 dBm。
兩種架構匹配電路部分皆作在晶片外，採用高品質因數的外部電感提高電壓的增益，藉此極高靈敏度。

This thesis presents the implementation of an ultra-low power wake-up receiver operating in the Industrial Scientific Band (ISM) and capable of receiving and demodulating On-Off Keying (OOK) signals. The design is fabricated using TSMC's 0.18-micron CMOS process. Two chips are implemented in the wake-up receiver architecture. The first chip serves as the envelope detector and the first stage of the wake-up receiver. Although this architecture achieves ultra-low power consumption, the overall sensitivity is limited by the envelope detector. To enhance the detector's conversion gain and improve sensitivity, a dynamic body-biasing compensation technique is employed. AC coupling is utilized to separate the detector from the subsequent stages, considering that the wake-up receiver operates without input signals for most of the time. However, environmental interference during the waiting period for the wake-up code can lead to false alarms. To mitigate this, adjustable threshold architectures are employed in the comparator and correlator to resist environmental interference and facilitate successful generation of the wake-up signal. The target wake-up code and comparator thresholds are set by a digitally synthesized SPI circuit. The first chip operates at a supply voltage of 0.6 V, with a power consumption of 10 nW and a sensitivity of -67 dBm.
The second chip further improves sensitivity based on the first chip. Two main modifications are made. Firstly, the selection method for the detector stage in the first chip is adjusted, and the gate biased voltage of the transistors is optimized, thus the vdd is changed to 1 V, and enhance the passive gain of the matching circuit and optimize the signal-to-noise ratio of the detector output. Secondly, due to the drawbacks of using AC coupling capacitors in the first chip, such as high-pass effects caused by the coupling capacitors and the input impedance of the subsequent stage, a large coupling capacitor is required to avoid attenuation of the detector output. However, a large capacitance affects system settling time and limits the data rate. To overcome this, a common-mode feedback circuit is employed to establish a DC bias between system blocks, replacing the original AC coupling capacitors. The second chip adopts the same comparator and correlator as the first chip. Overall, the power consumption of the system is 40.7 nW when powered by a 1 V supply, with a sensitivity of -81.5 dBm.
The matching circuits in both architectures are implemented externally using high-quality factor external inductors to enhance voltage gain and achieve extremely high sensitivity.

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