在積體電路製程中，常常需要在晶圓上做出細微尺寸的圖案，而這些圖案的形成方式，乃是使用蝕刻技術，將微影技術所產生的光阻圖案，無誤的轉移到光阻底下的材質上。所謂的蝕刻技術，包含了所有將材質整面均勻移除的等向性蝕刻，或是有圖案的選擇性部分去除之非等向性蝕刻。而接觸層電漿蝕刻製程即是屬於非等向性蝕刻。在製程線寬越縮越小的情況下，如何有效且快速的控制接觸層線寬也就更顯得重要。
本文主要研究底層抗反射介電覆膜，蝕刻程式參數變化對接觸層線寬的調整能力。其內容在研究不同的C4F8氣體流量、製程時間與製程壓力條件下。對接觸層線寬的調整效果，並且從線寬與晶圓電性測試的結果分析其相關性。
實驗結果顯示，在氣體C4F8原始12sccm條件下，氣體流量增加1sccm對接觸層線寬約減小1.14nm(約1.6%) ;在製程時間原始120秒條件下，製程時間減少6秒對接觸層線寬約減小0.76nm(約1.06%) ;在製程壓力原始130mTorr條件下，製程壓力增加10mTorr對接觸層線寬約減小0.34nm(約0.47%)。另外線寬每減小1nm，電性接觸電阻的阻值增加0.76Ω。
從上述實驗結果可定論，抗反射介電覆膜蝕刻程式參數影響接觸層線寬最大的是C4F8氣體流量及製程時間，再來是製程壓力。線寬越小電性測試的接觸電阻阻值越大。

In the integrated circuit manufacturing process, Patterns of small sizes often needs to be formed on the wafer. The method of pattern formation is to use developers to remove the exposure photo resist so that pattern can be directly transferred to wafer. Etching method is the technology used, including isotropic etching and non-isotropic etching. The contact plasma etching process is a non-isotropic etching. As the process pattern dimension shrinks gradually, it is important to know how to control the contact line width effectively and fast.
In this study, the change of bottom antireflective coating etching recipe parameter to adjust the contact line width is the main focus. Comparing parameter change along with the contact line width, three factors are considered, namely differences of C4F8 flow, process time, and process pressure. Furthermore, the correlation between contact line width and wafer electrical test result is also analyzed.
According to the experiment results, firstly increasing the C4F8 gas flow by 1 sccm from 12sccm, decreases the line width approximately 1.14nm (~1.6%); Secondly, increasing process time by 6 seconds from 120seconds, decreases the line width approximately 0.76nm(~1.06%); Lastly, increasing the process pressure by 10mTorr from 130mTorr, decreases the line width approximately 0.34nm(~0.47%).Decreasing the contact line width by 1nm will cause wafer electrical test contact resistance to increase by0.76Ω
From the results above, it can be concluded that C4F8 gas flow and process time is the key factor for line width regulation, then the process finally by the pressure. The smaller line width is higher electrical test resistance presents.

1.Hong Xiao原著,羅正中、張鼎張譯, 半導體技術導論,學銘圖書有限公司(2002).
2.莊達人，“VLSI 製造技術”，高立出版社，(1996).
3.D. M. Manos and D. L. Flamm, Plasma Etching, An Introduction, Academic Press, san Diego, CA,(1989).
4.I. Morey and A. Asthana, “Etch challenges of low-k dielectric,” Solid State Technology,Vol.42, No6, p.71(1999).
5.D. G. Baldwin, M. E. Williams, and P. L. Murphy, “Chemical Safety Handbook for the Semiconductor/Electronics Industry,” 2d ed., OME Press, Beveriy, MA,(1996).
6.R. Bowman, G. Fry, J. Griffin, D. Potter, and R. Skinner, “Practical VLSI Fabrication for the 90s,” Integrated Circuit Engineering Corporation,(1990).
7.張俊彥，“積體電路製程及設備技術手冊”，經濟部技術處(1997).
8.C. Y. Chang, and S. M. Sue, “ULSI Technology,” McGraw-Hill Company publication, New York, (1996).
9.A. Grill “Cold plasma in material fabrication” New York : IEEE(1994).
10.S. Kleditzsch and U. Riedel “Sensitivity of silicon etching in chlorine/argon plasma” J.Vac. Sci.Techol. A 18(5),pp.2130 (2000).
11.P. Werbaneth and J. Alrnetico, “STI etch in Cl2-Ar plasmas ” Solid State Technology,pp.87 (2000).
12.S. Nakaoka, H. Watanabe, and Y. Okuda, “Comparison of CD variation between organic and inorganic bottom anti-reflective coating on topographic substrates,” Proc. of SPIE, Vol.3679 pp.932-941. (1999).
13.莊怡芬，真空紫外微影技術底抗反射層及Fabry-Perot 型光罩抗反射層之研究，中央大學光電科學研究所碩士論文(2002).
14.P. Trefonas, R. Blacksmith, C. R. Szmanda, R. Kavanagh, Tim Adams,
G. N. Taylor, S. Coley, and G. Pohlers, “Organic antireflective coatings for 193 nm lithography ” Proc. of SPIE, Vol. 3678 pp.702-712(1999).
15.C. H. Lin, L. A. Wang, and H. L. Chen, “Optimized bilayer hexamethyldisiloxane film as bottom antireflective coating for both
KrF and ArF lithographies,” J. Vac. Sci. Technol. B, Vol. 18, No. 6
pp.3323-3327(2000).
16.J. C. Cox, L. Welsh, D. Murphy, “Process effects resulting from conversion to a safe-solvent organic BARC,” Proc. Of SPIE, Vol. 3333 pp.1040-1050(1998).
17.Y. Trouiller, N. Buffet, T. Mourier, Y. Gobil, P. Schiavone,and Y.
Quere,“Inorganic bottom ARC SiOxNy for interconnection levels on
0.18μm technology,” Proc. of SPIE, Vol. 3333 pp.324-333 (1998).
18.H.L. Chen and L. A.Wang, “Hexamethyldisiloxane film as the bottom antireflective coating layer for ArF excimer laser lithography,” Applied Optics, Vol. 38 pp.4885-4890(1999).
19.R. Yamanaka, T. Hattori, T. Mine, K. Hattori, O. Tanaka and T. Terasawa, “Suppression of resist-pattern deformation on SiON bottom antireflective layer in deep-UV lithography” Proc. of SPIE, Vol. 3678 pp.198-204. (1999).
20.E. Iguchi, H. Komano and T. Nakayama, “A new bottom anti-reflection
coating approach for KrF lithography at sub 150 nm design rule,” Proc. of SPIE, Vol. 3999 pp.521-530 (2000).
21.J. D. Meador, X. Shao, V. Krishnamurthy, M. Arjona, M. Bhave, G. Xu, J. Claypool, and A. Lindgren,“Second-generation 193nm bottom antireflective coatings (BARCs)” Proc. of SPIE, Vol. 3999 pp.1009-1018(2000).
22.龍文安，“積體電路微影製程”初版，高力， pp.288(1998).
23.T. S. Yen and E. S. Jeng “Method for controlling line width by etching bottom anti-reflective coating” Vanguard International Semiconductor Corporation (Hsin-Chu, TW), United States Patent 5962195(1999).
24.H. M. Park, D. S. Grimard, J. W. Grizzle and F. L. Terry “Etching profile control of high-aspect ratio deep submicrometer a-Si gate etch” IEEE Trans. Semiconduct. Manufact.,Vol 14,pp.242(2001).
25.郭建億，深次微米世代微影術底部抗反射層與奈米粒子選區成長之研究，國立清華大學生醫工程與環境科學系碩士論文(2003).
26.J.M. Lane, K.H.A. Bogart, F.P. Klemens, and J,T.C. Lee, “The role of
feed gas chemistry, mask material, and processing parameters in profile evolution during etching of Si(100) ”J.Vac.Sci.Techol. A 18(5),pp.2067 (2000).
27.P. L. Jones , M. S. Chang , S. Bell “Etch process for CD reduction of arc material” Advanced Micro Devices, Inc. (Sunnyvale, CA, US), United States Patent 7361588(2008).
28.C. K. Liu , C. J. Shieh , P. H. Chen “Plasma etch method for forming patterned layer with enhanced critical dimension(CD)control” Taiwan
Semiconductor Manufacturing Company, LTD (Hsin Chu, TW), United States Patent 6350390(2002).
29.K.H.A. Bogart, F.P. Klemens, M.V. Malyshev, J.I. Colonell,V.M/ Donnelly J,T.C. Lee and J.M. Lane, “Mask charging and profile evolution during chlorine plasma etching of silicon” J.Vac.Sci. Techol. A18(1),pp.197 (2000).
30.P. Jiang , R. Kraft , M. Somervell “BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control” Texas Instruments Incorporated (Dallas, TX, US). United States Patent 6900123(2005).
31.J. B. Friedmann , C. C. Baum “Method for BARC over-etch time adjust
with real-time process feedback” Texas Instruments Incorporated (Dallas, TX, US), United States Patent 6979648(2005).
32.張秋貴，應用實驗設計法調整蝕刻製程程式以改善晶圓允收測試之接觸窗阻值電性之研究，中原大學工業工程研究所碩士論文(2003).
33.C. K. Yeon and H. J. You ,”Deep-submicron trench profile control using a magnetron enhanced reactive ion etching system for shallow trench isolation” J.Vac.Sci. Techol. A 16(3),pp.1502 (1998).
34.K.H.A.Bogart and V.M.Donnelly “On the constant composition and thickness of the chlorinated silicon surface layer subjected to increasing etching product concentrations during chlorine plasma etching”J. Appl. Phys.,86 ,pp.1822 (1999).
35.D. J. Guerrero, J. Lowes and R. Mercado: “Organic monolayer determination on semiconductor substrates” Journal of Photopolymer Science and Technology, Vol. 20, pp.339-343 (2007).
36.J. K. Schneider, Y. Xiao and A. Gerardo “Organic barc etch process capable of use in the formation of low K dual damascene integrated circuits” BALZAN, Christopher R.; 674 County Square Drive (US). WO 2007/123616 A2 (2007).