| 研究生: |
厲秉杰 Li, Bing-Jie |
|---|---|
| 論文名稱: |
研究導入富勒烯衍生物在介電層對五苯環電晶體的記憶效應影響 Study of a fullerene derivative for use in pentacene-based thin-film transistor-type memory devices |
| 指導教授: |
鄭弘隆
Cheng, Horng-Long |
| 學位類別: |
碩士 Master |
| 系所名稱: |
理學院 - 光電科學與工程學系 Department of Photonics |
| 論文出版年: | 2019 |
| 畢業學年度: | 107 |
| 語文別: | 中文 |
| 論文頁數: | 73 |
| 中文關鍵詞: | 富勒烯衍生物 、五苯環 、High-K材料 、有機薄膜電晶體 、記憶效應 、複合薄膜 |
| 外文關鍵詞: | fullerene derivative, pentacene, High-K materials, organic thin-film transistors, memory window |
| 相關次數: | 點閱:112 下載:2 |
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本論文使用氧化鋁/聚醯亞胺(Polyimide,PI)雙層薄膜為介電層,製作可低電壓操作之五苯環(pentacene) 有機薄膜電晶體式記憶元件,研究導入 [6,6]-phenyl-C61-butyric acid methyl ester (PCBM)於介電層PI對元件的記憶效應的影響 。故本論文進一步探討PCBM混摻修飾PI層之五苯環電晶體記憶效應是否為PI溶液濃度稀釋、PCBM載子陷補抑或是上述兩者共同影響,及對比PCBM修飾PI層表面和混摻修飾PI層之五苯環電晶體。以半導體參數分析儀比較不同修飾層參數之五苯環電晶體相關記憶效應,利用表面接觸角分析儀、原子力顯微鏡與掃描式開爾文探針顯微鏡,探討PCBM於於修飾層結構中的分佈位置與介面寫入效應。
經實驗後,發現PCBM混摻修飾PI層之五苯環電晶體利用PCBM之電子受體特性具有記憶效應,與PI溶液濃度稀釋之五苯環電晶體受閘極偏壓控制能力增強具記憶效應原理不同。PCBM修飾PI層表面之五苯環電晶體亦可得寫入區間 。為了驗證PCBM混摻修飾結構之PCBM於修飾層與主動層介面分佈,可由PCBM修飾PI層表面與混摻修飾PI層結構之薄膜表面能極性項與表面電位皆下降特性,推得PCBM分佈於修飾層PI表面,且驗證記憶寫入效應來自於PCBM與五苯環介面缺陷的載子陷補作用。
進行記憶元件訊號清除時,使用PCBM進行混摻或修飾PI層表面之五苯環電晶體皆可單獨利用照光達到清除效果,由於不需外加清除電壓,此舉有助降低元件功耗。可由照光電容之電荷提早累積印證臨界電壓往原點偏移,以及缺陷能態密度增長率減小,鬆弛時間變短得證。且pentacene對介面載子清除能力不受PCBM修飾PI層表面或混摻結構影響。在多次寫入清除操作下,二者元件皆可穩定操作且保有一定記憶窗口。
根據上述結果知可用PCBM修飾PI作為記憶元件之駐極體層,並以五苯環與氧化鋁達成低功耗元件之需求。
Thin-film transistor-type organic memory devices have high potential for applications in wearable devices or unmanned vehicles that feature low power consumption and detection ability. In this study, thin-film transistor-type pentacene-based memory devices were fabricated. [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) was used to modify the polyimide (PI) dielectric layer. The role of PCBM in the electrical performance of pentacene-based memory devices was also investigated.
Three kinds of solution-processing dielectric layers of memory devices, including the single PI layer (Device A), the PI:PCBM blending layer (Device B), and the PI/PCBM bilayer (Device C), were prepared. Device A showed a low programming threshold voltage of 0.1 V. Device B performed a small subthreshold swing (s.s.) of 0.16 V/dec, a memory window (VM) of 0.49 V, and a low threshold voltage. Device C presented a small s.s. of 0.19 V/dec and a large VM of 0.89 V. Experimental results indicated that the PCBM-modified PI dielectric layer could increase the memory window of pentacene-based memory devices. The charge erasing capability of Devices B and C could be achieved by laser irradiation without bias voltage, which is beneficial for the decrease in the device’s power consumption.
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校內:2024-01-01公開