本論文提出了一個新型的雙層電阻式隨機存取記憶體模型，並探討了其在記憶體內運算應用中的潛力和優化策略，為未來高效能、低功耗的神經型態計算系統的設計和實現提供預測及評估。
首先，本論文聚焦於具有雙層氧化層結構的電阻式隨機存取記憶體，深入探討其獨特的雙層特性：一層易於阻態切換，另一層則相對穩定。這種結構為電阻式隨機存取記憶體的性能優化和應用拓展提供了新的可能性。本研究分析了不同元件參數對於電性的影響，並以此為基礎，採用漸進式方法開發了雙層電阻式隨機存取記憶體精簡模型。為了實現模型的實用性和可擴展性，我們採用了相容於SPICE之硬體描述語言Verilog-A，提高了其應用價值。模型將物理傳輸機制與導電絲調變機制結合，在能夠呈現出電阻式隨機存取記憶體的高低阻態切換行為時，還能捕捉其電流非線性度和脈波阻值調變的線性特性。本研究之關鍵貢獻是這一模型的獨特之處在於其靈活性，能夠呈現出元件在各種操作條件下之電氣特性，為類神經網路應用進行舖墊。
隨著人工智慧和深度學習技術的快速發展，傳統的馮鈕曼架構在處理深度神經網路時面臨著嚴重的效能瓶頸。為應對這一挑戰，本研究探討了電阻式隨機存取記憶體從儲存方案延伸至記憶體內運算應用的轉變，並利用這一精簡模型，我們進行了包括元件變異度以及記憶體陣列中寄生電阻造成的電流誤差評估，將此結果進行萃取後，進一步利用PyTorch建立之記憶體內運算模擬平台，分析和預測記憶體內運算應用中的硬體誤差對神經網路辨識準確率的影響，為元件操作與演算法之協同優化(co-optimization)提供見解。

This dissertation presents a novel bilayer resistive random-access memory (RRAM) model and explores its potential and optimization strategies in Compute-in-Memory (CIM) applications, providing predictions and evaluations for the design and implementation of future high-performance, low-power neuromorphic computing systems.
This research investigates RRAM featuring a bilayer oxide structure, examining its distinctive dual-layer characteristics, where one layer exhibits resistance switching properties while the other maintains relative stability. This structure opens new possibil-ities for RRAM performance optimization and further application expansion. This study systematically analyzes the impact of various device parameters on electrical properties, utilizing these insights to develop a compact bilayer RRAM model through a progressive modeling approach. To ensure the model's practicality and scalability, we employed the SPICE compatible hardware description language Verilog-A, thus enhancing its appli-cation value. The model integrates physical transport mechanisms with conductive fila-ment modulation mechanisms, capturing not only the high and low resistance state switching behavior of RRAM but also its “current non-linearity” and the “potentia-tion/depression linearity” by pulse-based resistance modulation. A key contribution of this research is the model's flexibility, capable of representing device electrical characteristics under various conditions, laying the groundwork for neural network applications.
The escalating demand for artificial intelligence (AI) and deep learning capabilities has exposed significant performance limitations in conventional von Neumann archi-tectures when handling large-scale neural networks. To address this challenge, our re-search explores the transition of RRAM from storage solutions to Compute-in-Memory (CIM) applications. Utilizing this compact model, we conducted evaluations including device variability and current summation error assessment due to parasitic resistances in memory arrays. After extracting these results, we further employed a CIM simulation platform built with PyTorch to analyze and predict the impact of hardware errors in CIM applications on neural network recognition accuracy. This provides crucial insights for the co-optimization of device operation and algorithms.

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