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研究生: 陳楷棋
Chen, Kai-Chi
論文名稱: 不同摻雜濃度及汲極/源極厚度對無接面堆疊式反相器電壓轉換特性之影響
A Study of Vertically Stacked Junctionless Nanosheet Complementary Metal-Oxide-Semiconductor with Different Dopant Concentration and Raised Source/Drain
指導教授: 李文熙
Lee, Wen-Hsi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2023
畢業學年度: 111
語文別: 中文
論文頁數: 83
中文關鍵詞: 抬升式源汲極奈米薄片環繞式閘極無接面式電晶體互補式金屬氧化物半導體
外文關鍵詞: CFET, junctionless, vertically stacked, nanosheet, Gate-All-Around
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  • 目錄 摘要 II 誌謝 XIII 表目錄 XVI 圖目錄 XVII 第1章 緒論 1 1.1 離子佈植Ion Implantation 1 1.2 退火Annealing 2 1.3 無接面場效電晶體Junctionless FET 3 1.4 互補式金屬氧化物半導體反相器CMOS inverter 6 1.5 環繞式閘極奈米片Gate-All-Around Nanosheet 9 1.6 互補場效電晶體CFET 11 1.7 研究動機與目的 13 第2章 實驗方法 15 2.1 上下層通道堆疊 16 2.2 主動區與閘極定義 20 2.3 鈍化層與金屬連線 28 2.4 元件量測與參數萃取 32 2.4.1 臨界電壓(Threshold Voltage; Vth) 32 2.4.2 次臨界擺幅(Subthreshold Swing; SS) 33 2.4.3 汲極引發位能障下降(Drain Induce Barrier Lowing; DIBL) 33 2.4.4 電流開關比(On/Off Current Ratio; Ion/Ioff) 34 2.4.5 轉導(Transconductance; Gm) 34 第3章 結果與討論 37 3.1 通道寬度對於nFETs與pFETs ID-VG特性影響 37 3.2 摻雜濃度與源汲極厚度對元件特性影響 46 3.3 TLM與SIMS分析 49 3.4 CFET 反相器 VTC特性 54 第4章 結論與未來展望 59 4.1 結論 59 4.2 未來展望 60 參考文獻 61

    1. Seong-Yeon Kim, Byung-Hyun Lee, Jae Hur, Jun-Young Park, “A Comparative Study on Hot-Carrier Injection in 5-Story Vertically Integrated Inversion-Mode and Junctionless-Mode Gate-All-Around MOSFETs” IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 1, JANUARY 2018.
    2. Po-Jung Sung, Shu-Wei Chang, Kuo-Hsing Kao, Member, IEEE, Chien-Ting Wu, Chun-Jung Su, Ta-Chun Cho, Fu-Kuo Hsueh, Wen-Hsi Lee, Yao-Jen Lee,“Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 9, SEPTEMBER 2020.
    3. S.-W. Chang, P.-J. Sung, T-Y. Chu, D. D. Lu, C. -J. Wang, N.-C. Lin1, C.-J. Su1, S.-H. Lo, H.-F. Huang, J.-H. Li, M.-K. Huang, Y.-C. Huang, S.-T. Huang, H.-C. Wang, Y.-J. Huang, J.-Y. Wang, L.-W Yu, Y.-F. Huang, F.-K. Hsueh, C.-T. Wu, W. C.-Y. Ma, K.-H. Kao, Y.-J. Lee, C.-L. Lin, R.W. Chuang, K.-P. Huang, S. Samukawa, Y. Li, W.-H. Lee, T.-S. Chao, G.-W. Huang, W.-F. Wu, J.-Y. Li, J.-M. Shieh, W. -K. Yeh, Y.-H. Wang, “First_Demonstration_of_CMOS_Inverter_and_6T-SRAM_Based_on_GAA_CFETs_Structure_for_3D-IC_Applications” 2019 IEEE International Electron Devices Meeting (IEDM)
    4. Feng-Tso Chien, Member, IEEE, Chii-Wen Chen, Tien-Chun Lee, Chi-Ling Wang, Ching-Hwa Cheng, Tsung-Kuei Kang, and Hsien-Chin Chiu, “A Novel Self-Aligned Double-Channel Polysilicon Thin-Film Transistor” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013.
    5. Kow Ming Chang, Gin Min Lin, Cheng Guo Chen, and Mon Fan Hsieh, “Polycrystalline silicon thin-film transistor with self-aligned SiGe raised sourceÕdrain” IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 1, JANUARY 2007.
    6. 蕭宏, ”半導體製程技術導論(第三版)”全華圖書股份有限公司,APRIL 2021
    7. Sheng-Ti Chung, Yao-Jen Lee, and Tien-Sheng Chao, “Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas Annealing” IEEE TRANSACTIONS ON NANOTECHNOLOGY, Volume 19, 2020.
    8. Manuel Aldegunde, Antonio Martinez, and John R. Barker, “Study of Discrete Doping-Induced Variability in Junctionless Nanowire MOSFETs Using Dissipative Quantum Transport Simulations” IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 2, FEBRUARY 2012
    9. Ming-Hung Han, Chun-Yen Chang, Life Fellow, IEEE, Yi-Ruei Jhan, Jia-Jiun Wu, Hung-Bin Chen, Ya-Chi Cheng, and Yung-Chun Wu, “Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis” IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 2, FEBRUARY 2013
    10. Greg Leung, “Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs” IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 6, JUNE 2012
    11. J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi “Junctionless Nanowire Transistor (JNT): Properties and Design Guidelines” Solid-State Electronics 65–66 (2011) 33–37
    12. Adrian M. Ionescu “Nanowire transistors made easy” nature nanotechnology | VOL 5 | MARCH 2010
    13. S.Subramanian et al. “First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers” 2020 Symposium on VLSI Technology Digest of Technical Papers
    14. https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap?fbclid=IwAR22CYHG1vzfqrKBv_jecYZ5EdDipmwYW6GNuQyflYnx3iKaK9zNQsI45dU
    15. P. Schuddinck et al. “PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch” 2022 IEEE Symposium on VLSI Technology and Circuits
    16. A. Ortiz-Conde et al. “A review of recent MOSFET threshold voltage extraction methods” Microelectronics Reliability 42 (2002) 583–596
    17. B. VINCENT et al. “A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options Done by Virtual Fabrication” IEEE Journal of the Electron Devices Society(Volume: 8) 28 April 2020
    18. A. Mocuta et al. “Enabling CMOS Scaling Towards 3nm and Beyond” 2018 Symposium on VLSI Technology Digest of Technical Papers
    19. J. Ryckaert et al. “Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!” 2019 IEEE International Electron Devices Meeting (IEDM)
    20. S. B. Samavedam et al. “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips” 2020 IEEE International Electron Devices Meeting (IEDM)
    21. P. Weckx et al. “Novel forksheet device architecture as ultimate logic scaling device towards 2nm” 2019 IEEE International Electron Devices Meeting (IEDM)
    22. SEUNG-GEUN JUNG et al. “Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET” 20 December 2021 IEEE Journal of the Electron Devices Society(Volume: 10)
    23. Ryckaert J. et al. “The Complementary FET (CFET) for CMOS scaling beyond N3” 2018 IEEE Symposium on VLSI Technology
    24. P. Schuddinck et al. “PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch” 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
    25. Horng-Chih Lin et al. “Fabrication and Characterization of Nanowire Transistors With Solid-Phase Crystallized Poly-Si Channels” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 10, OCTOBER 2006
    26. Donald A. Neamen. “Semiconductor physics and devices: basic principles”, Fourth Edition New York: McGraw-Hill,2012
    27. Samsung,”https://news.samsung.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture”
    28. M.I. Current, “Basics of ion implantation”, Ion beam press.TX, 1997
    29. TSRI https://www.tsri.org.tw/tw/commonPage.jsp?kindId=E0015
    30. Horng-Chih Lin et al. “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013
    31. Shinji Migita et al. “Electrical Performances of Junctionless-FETs at the Scaling Limit (LCH = 3 nm)” 2012 International Electron Devices Meeting
    32. C. -Y. Huang et al. “3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling” 2020 IEEE International Electron Devices Meeting (IEDM)
    33. A. Veloso et al. “Nanowire & Nanosheet FETs for Ultra-Scaled, High-Density Logic and Memory Applications” 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
    34. Donald A.Neamen,” Microelectronics circuit analysis and design” 4th ed. McGraw-Hill 2009
    35. Xinghao Chen et al.” Fundamentals of CMOS design” 2009
    36. Seong Kwang Kim et al. “Heterogeneous 3D Sequential CFET with Ge (110) Nanosheet p-FET on Si (100) bulk n-FET by Direct Wafer Bonding” 2022 IEEE International Electron Devices Meeting (IEDM)

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