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研究生：	孫慶儒 Sun, Ching-Ju
論文名稱：	以FPGA實現一支援高階語言的RISC-V電腦系統 FPGA Implementation of a RISC-V Computer System with High-Level Language Support
指導教授：	陳進興 Chen, Chin-Hsing 張名先 Chang, Ming-Xian
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2024
畢業學年度：	112
語文別：	英文
論文頁數：	80
中文關鍵詞：	現場可規劃邏輯電路、RISC-V 、編譯器、組譯器、記憶體階層、RS232
外文關鍵詞：	field programmable logic gate array (FPGA), RISC-V, Compiler, Assembler, Memory Hierarchy, RS232
相關次數：	點閱：57 下載：11
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隨著科技的發展，人工智慧所需的運算能力越來越龐大，為了因應這要求，高效能處理器想必是非常重要。那在現今這麼多處理器中，其中以RISC-V架構處理器較為突出。它的優點在於開放和靈活性的設計，可依使用者自訂，滿足特別的需求。因其簡潔有效的指令和設計，這也使得實現低功耗且高效能的處理器成為可能。本論文以RV32IM指令集去設計帶有快取記憶體的RISC-V五級流水線架構處理器實現於FPGA系統。

本論文將以C語言編寫的程式，經過RISC-V編譯器及組譯器轉換成機器語言，將它從電腦端透過RS232串接口輸入FPGA中，經過RISC-V處理器的運算，將得出的結果從記憶體中讀出，透過RS232串接口輸出到電腦端，並在螢幕上顯示。

使用快取記憶體與沒有使用快取記憶體之RISC-V架構處理器相比較，因為記憶體階層的特性，前者具有讀寫速度快的優點，其得出結果的速度較沒有使用快取記憶體之RISC-V架構處理器快了4倍，驗證了記憶體階層的特性。我們還實現了區塊版本的矩陣乘法。我們發現區塊版本的資料快取命中率高於原始版本。這可以在資料被替換之前，最大化對已載入快取中的資料的存取，即改善時間局部性以減少快取未命中。

With the advancement of technology, artificial intelligence requires powerful computing capabilities. In response to this demand, efficient processors are undoubtedly crucial. Among the multitude of processors available today, RISC-V architecture processors stand out prominently. Their advantages lie in their open and flexible design, allowing customization to meet specific needs. Additionally, their concise and effective instruction set design enables the realization of low-power and high-performance processors. This thesis designs a RISC-V five-stage pipelined architecture processor with cache memory implemented on an FPGA system, using the RV32IM instruction set.

This thesis wrote program in C language, which was compiled and assembled into machine code using a RISC-V compiler and assembler. The program then was inputted into the FPGA through the RS232 serial interface from the computer. After undergoing computation by the RISC-V processor, the resulting output was read from the memory and outputted back to the computer via the RS232 serial interface, displaying the results on the screen.

Comparing a RISC-V architecture processor with cache memory to one without cache memory, the former exhibits the advantage of faster read and write speeds due to the characteristics of memory hierarchy. As a result, the processor with cache memory achieves a speedup of 4 times compared to the one without cache memory in obtaining results. It verify the characteristics of memory hierarchy. We also implemented the blocking version of matrix multiplication. We found that blocking version data cache hit rate is higher than the original version. It maximize accesses to the data loaded into the cache before the data are replaced; that is, improve temporal locality to reduce cache misses.

摘要 I
Abstract III
誌謝 V
Acknowledgment VI
Contents VII
List of Tables IX
List of Figures X
Chapter 1 Introduction 1
1 RISC-V 1
2 Compiler/Assembler 2
3 Field Programmable Gate Array (FPGA) 3
4 Motivation and Contribution 6
5 Thesis Organization 7
Chapter 2 Fundamentals and Related Work 8
1 RISC-V Instruction Set Architecture (ISA) 8
1.1 Modular Instruction Set 8
1.2 Register Specification 10
1.3 Instruction Format 11
2 Memory Hierarchy 17
3 Compiler/Assembler with Lex & Yacc 18
Chapter 3 Proposed Work 21
1 Implementation Method and Equipment 21
1.1 Method and Workflow 21
1.2 DE2-115 Development Board 23
1.3 Programming Interface 24
1.4 RS232 Interface 24
2 The Top-Level Module 25
3 RS232 Module 26
3.1 RS232 Receiver Module 26
3.2 RS232 Transmitter Module 27
4 Memory Control Module 28
4.1 Instruction Memory Control Module 28
4.2 Data Memory Control Module 29
5 Cache Control Module 30
5.1 Instruction Cache Control Module 31
5.2 Data Cache Control Module 32
6 RISC-V Processor Module 33
Chapter 4 Experimental Results 36
1 Research Equipment and Environment 36
2 Test Pattern for Checking Register and Memory 40
3 Test Pattern for Checking Cache Hit/Miss 48
4 Matrix Multiplication 56
5 The resources of FPGA used by the Proposed System 60
Chapter 5 Conclusion and Future Work 61
1 Conclusion 61
2 Future Work 62
References 64
                                    

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