現實中的影像常會因為各種原因產生許多雜訊，這些雜訊會常會干擾到影像的利用，所以去雜訊對於影像處理的應用是一個很重要的技術。在去雜訊的技術之中，有一個很重要的問題是，如何在去除雜訊的同時，又不破壞影像的特徵。而在眾多的去雜訊技術裡，雙邊濾波(bilateral filtering)是一個在影像處理領域裡很廣為人知的一項去雜訊技術。雙邊濾波器的優點是在去除雜訊的同時還可以保留影像的邊緣細節，也因為這項性質，讓雙邊濾波器被應用在很多地方，而以雙邊濾波器為基礎的延伸方法也很多。
雙邊濾波器的運算複雜度很高，所以近年來有些研究提出雙邊濾波器的硬體實作來加快它的速度。雖然這些方法可以提高速度，但是他們的硬體電路成本都還有一些改善的空間。在本論文中，我們提出一個低成本且高速的雙邊濾波器的硬體架構。為了降低硬體成本，我們使用資料路徑最佳化(data path optimization)、資源共享(resource sharing)來減少乘法器的數量，並提出一個特殊設計的LUT(look up table)來減少所需要的記憶體空間。此硬體架構是以Verilog硬體描述實作，並使用Xilinx ISE 14.7 WebPACK版本來合成。實驗結果顯示，和現有文獻相比，我們的設計可以在不影響影像品質的前提下減少成本，而且在速度上也足以達到即時處理的目標。

Real-world images may be dominated by all kinds of noises due to many reasons. In most case, these noises will interfere with the usage of the images. Thus, the technology of noise reduction is very important in processing images. In the field of image noise reduction, there is a major concern in removing noises from the images and at the same time without damaging the characteristics of it. Among the technologies of noise reduction, bilateral filtering is the most well-known technique in the field of image processing. The major advantage of using the bilateral filter is that it removes the noise from the images while retaining the details of the image’s edges. It is the reason why the bilateral filter is widely used and became the base form of many other extension methods.
In real time application, the computational complexity of the bilateral filter is very high. So in recent years, some studies have proposed a hardware implementation of bilateral filter in order to improve its speed. Although these methods are able to improve the speed of processing, however their hardware cost could be further improved. In this thesis, a low-cost and real-time VLSI architecture is proposed. Data path optimization and resource sharing were applied to reduce the number of multipliers. In addition, a special purpose look-up table is proposed to reduce the required memory space. As a result, the cost of hardware is reduced. The VLSI architecture is implemented by using Verilog hardware description language and synthesized by using Xilinx ISE 14.7 WebPACK version. According to our experimental results, the proposed design reduces the cost of hardware without compromising the image quality in comparison with the existing literature. Besides that, it is able to achieve real-time processing.

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