現今電子消費市場可明顯看出通訊、數據、影音等許多功能已整合進單一裝置，以智慧型手機為例，手機整合各種晶片來處理多媒體應用，如錄影、照相、微型投影和擴增實境(Augmented Reality，AR)。加上4G/WIFI/LTE無線寬頻技術的快速發展，對於資料傳輸的頻寬要求比起以往強烈許多。

同時，在電信、娛樂多媒體或手持行動裝置領域上，隨著半導體技術的持續成長，眾多矽智財(silicon intellectual property，SIP)供應商致力於開發多功能、高效能且省電的矽智財，如DSP、GPU、WIFI，其可重複使用(reusable)、可修改(programmable)的模組特性，大幅縮短系統單晶片(System-on-Chip，SoC)的設計時程。然而矽智財供應商卻面臨了難題，矽智財能否在各種環境中相容。當系統設計者希望快速整合各種矽智財時，定義一種標準匯流排協定即成為了最有效率的方法，讓矽智財供應商生產的矽智財具有可攜性(portable)。

嵌入式系統整合軟體、硬體與行動應用，系統底層以匯流排負責各個矽智財的溝通，為了創造流暢的使用者體驗(User Experience)，高效率的匯流排是設計系統單晶片的關鍵。總結前段所述，如何讓矽智財之間相容、快速傳遞封包並且合理的區域化分配，是當前匯流排的重要議題。

如今系統單晶片整合越來越多矽智財，匯流排擴充性及特定矽智財的高效能需求，成為傳統匯流排面臨的挑戰。根據本實驗室學長的提出的Mercurius高速匯流排架構，其交易效能比傳統匯流排快三倍，本作除了利用完整的嵌入式系統驗證外，也進一步改善前作的功能與效能，在一般交通流量下使效能提升到傳統匯流排的五倍，並設計應用於網路式晶片(Network on Chip)的路由核心(router core)，稱之AnyNoC，其具有前作的低延遲、高傳輸量、擴充性。以虛擬點對點(virtual point-to-point)的封包傳輸通道，同時接收所有輸入埠(ingress port)的資料，且立即傳送所有封包至輸出埠(egress port)，避免多個裝置進行存取時的匯流排競爭，大幅提升矽智財之間的頻寬。路由核心使用共享式記憶體輸出佇列封包交換技術(shared-memory output-queue packet switching)來充份利用封包緩衝區。輸出佇列架構可以消除前端緩衝佇列阻塞效應(HOL blocking)，並支援多筆資料交易(multiple outstanding transaction)，使系統效能達到最佳。流量控制(flow control)模組不僅在公平分配系統資源之下避免封包緩衝區溢出，更有效利用封包緩衝區，並提升系統單晶片上的服務品質(quality of service，QoS)。

本作AnyNoC中的連接設定上，相鄰的路由核心之間使用封包式傳輸，並利用適合的網路介面(network interface，NI)支援各種通訊協定(AHB、AXI、OCP)的矽智財。AnyNoC的多網段(network segment)架構可彈性擴充大量的矽智財或匯流排，在單一晶片中建立全域非同步及區域同步(globally asynchronous locally synchronous，GALS)時脈系統；各個路由核心與網路介面分別具有獨立時脈；核心與裝置之間是透過交握(handshaking)方式來互相溝通，大幅降低網路時脈樹(clock tree)結構的複雜度，亦使整體時脈樹功耗更低。且交握方式的非同步電路防止大型系統單晶片下的時鐘傾斜(clock skew)，並利用非同步(asynchronous)資料緩衝區來防止因為不同時脈溝通時產生的亞穩態(metastable)輸出。

In this paper, the performance of a packet switched router is improved by
means of a shared-memory output-queue technique. The enhanced router not only has the benefits of good scalability and a high resource utilization
efficiency, but also offers a superior communication performance due to its
virtual point-to-point characteristic. In the proposed router, a virtual point-to-point connection is set up at each dedicated port; thus yielding a higher throughput without interrupting the slower devices or causing congestion at any of the other ports. In addition, the head-of-line (HOL) blocking problem is resolved by using a flit buffer to construct an output queued switch. In implementing the flit buffer, the buffer address is maintained by a dynamic linked list; thereby avoiding packet losses with flow control. The packet switched router is implemented in two different environments. In the first case, the router is implemented in a real-time embedded system in place of the traditional shared bus (e.g., the AHB bus).In the second case, the proposed router is used to construct a network-on-chip (NoC). The performance of the proposed router, designated as AnyNoC is evaluated by comparing the overall system throughput of the constructed NoC with that obtained using a traditional packet-switched NoC. It is shown that AnyNoC yields a significant reduction in the network latency compared to that achieved using a traditional router architecture.

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