在本論文中，我們的利用矽鍺虛擬基板成長出N型應變矽金氧半場效電晶體(Strained-Si NMOSFET)，因為能帶分離與等效質量下降，伸張應變矽可以提高電子的移動率，然而使用傳統矽鍺虛擬基板伴隨的是線差排(threading dislocation)的產生以及閘極氧化層與矽通道介面的粗糙，藉著利用化學機械式研磨(Chemical Mechanical Polishing)成功地降低線差排的密度以及得到較平整的閘極氧化層與矽通道介面。因此更進一步的提升了直流特性表現。
　　此外，由於線差排無疑地會在氧化層與通道層介面產生多餘的缺陷，而且閘極氧化層與矽通道介面的粗糙也會使載子移動率發生擾動，而1/f雜訊對其敏感度甚佳。使用化學機械式研磨改善矽鍺虛擬基板的應變矽場效電晶體，因為擁有較低的線差排以及較高的載子移動率，因而獲得較佳的1/f雜訊表現，因而也可以從此處獲得磊晶層品質改善的證據。

　　In this thesis, the　strained-Si NMOSFETs structures are fabricated on the SiGe virtual substrate. Introduction of tensile strained-Si layer into Si-based structures is attributed to the fact that electron mobility can be enhanced due to energy band splitting and the reduction of effective mass. However, conventional SiGe virtual substrate usually accompanies the threading dislocation and the roughness of SiO2/Si interface. By utilizing the Chemical Mechanical Polishing technique (CMP), lower threading dislocation density and less interface roughness between SiO2 and Si are obtained. Consequently, DC performance has further been improved.
　　Additionally, roughness and the defect at interface between the channel and gate oxide generated by threading dislocation make the flicker noise performance worse. At the same way, observing the improvement of flicker noise property is also to prove the superiority of the application of CMP.

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