金氧半場效電晶體 (MOSFET) 尺寸逐年縮小, 將在傳統的矽基板電晶體將面臨嚴重的物理限制, 例如短通道效應。因此許多研究致力於解決短通道效應, 例如: FinFet、3D-IC 或是High K 材料。其中淺接面摻雜技術也是其解決短通道效應的方法之一。 若可以在MOSFET 的通道裡形成奈米級的摻雜深度並且降低摻雜製程中對矽晶格的破壞將可以大幅降低短通道效應。由許多文獻指出本篇論文使用的熱燈絲沉積系統是一種摻雜技術可以達到淺接面的摻雜深度並且達到對矽基板少量的摻雜破壞。
在此論文中以電漿輔助熱燈絲沉積系統製作N和P型的金氧半場效電晶體並探討不同燈絲溫度對電晶體有何電性的影響。本論文也將以HWCVD製作在SOI基板之MOSFET並探討漏電流效應。研究中發現越高的燈絲線溫將會影響臨界電壓以及次臨界擺幅, 藉由這兩種數據結果得出越高的線溫可以到達越深的摻雜深度。本篇論文N型和P型之MOSFET的最佳線溫為1800℃以及 1650℃, 此溫度下有較佳的次臨界擺幅與較低的漏電流。最終透過此製成方法成功將N和PMOSFET結合成互補式金氧半場效電晶體 (CMOS)。

As the MOSFET devices have been scaling down, short channel effects become serious problems for traditional bulk MOSFETs. As the result, alternative MOSFET structure has been proposed. Shallow doping profiles is a solution. Shallow doping profiles in drain and source and reducing implantation damage are the most popular methods to suppress short channel effect. In lots of research, HWCVD doping system was a choice we applied to reach the object
In this thesis, the P and N MOSFET devices on bulk-Si with HWCVD assistant ICP doping system were investigated and the characteristic and the reliability of device with various dopant wire temperature were discussed. Silicon-on-insulator was used to test reliability in this work. It is observed that the drain current, threshold voltage and off-state leakage current would be affected due to the difference of doping depth. The n-MOSFET and p-MOSFET device with 1800℃and 1650℃ catalysts temperature has batter characteristic such as lower leakage current and subthreshold swing. Eventually, we combined the p and n MOSFET to fabricate a Complementary Metal-Oxide-Semiconductor (CMOS) device.

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