CMOS影像感測器的市場勢必將持續擴大。為了因應市場需求，製造技術必須持續的進步，製程上許多的問題也因應而生。本研究利用有限元素分析評估CMOS影像感測器製程中出現的問題，將研究項目分為晶圓接合製程、薄膜結構堆疊製程與內連線結構製程等三項研究。 在晶圓接合製程研究中，將晶圓接合製程的晶圓對位問題，透過不同的晶圓接合座與製程參數來進行實驗觀察影響接合準確率的因素。實驗結果顯示晶圓偏移的形式可能由中心或外圍偏移，較小的頂柱下壓力量與較大的分離間隙對特殊形式的晶圓承接座有較顯著的影響。在薄膜結構堆疊製程研究中，利用有限元素分析模擬CMOS薄膜堆疊過程，探討漏電流和薄膜堆疊結構之間的關係，校正材料參數以提高模擬結果的準確性。模擬和實驗結果都證實了測量的漏電流和應力之間的正相關性，利用此關係我們可以改變薄膜堆疊的結構，以減少漏電流，從而提高感測器的壽命和可靠性。在內連線結構製程研究中，利用有限元素模擬分析內連線結構的裂紋和界面脫層。評估局部區域的模型，以數值模擬判斷發生脫層破壞之可能性。結果顯示不同材料和導線間的熱機械性能不匹配是產生高應力的重要因素，還發現選擇具有較高楊氏模量和較低熱膨脹係數的low-k材料可以避免引起高應力，最後以最小化應力值為目標，更改內連線結構的幾何參數，最佳化層內連線的結構。

Complementary metal-oxide semiconductor (CMOS) image sensors (CISs) are extensively used in devices such as notebook computers, digital cameras, mobile phones as well as in various other applications. As the manufacturing demand increases in the automotive industry, the market for CISs is bound to expand as well. To meet the market demand, the manufacturing technology must continue to progress, and many problems may arise during this progression. In this study, a finite element analysis (FEA) was used to evaluate the problems that arise in the CIS manufacturing process. The research items were divided into three subtopics: the wafer-bonding process, film-stack-architecture process, and multilevel-interconnect-structure process.
In the wafer bonding process, the experimental results show that the form of the wafer distortion may be caused by a shifted center or periphery. Additionally, in bond chuck type A, a smaller pin force and larger separation gap have a significant influence on the bonding accuracy. In the film-stack-architecture process, we simulate the CIS film stacking process using FEA. The simulated and experimental results confirm a positive correlation between the measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of CIS

components. In the multilevel-interconnect-structure process study, we use the finite element method to analyze the cracking and interfacial delamination of the interconnect structures. The results show that selecting low-k materials with high Young's modulus and low coefficients of thermal expansion could prevent the generation of high stress. Finally, to minimize stress in the device, the geometric parameters of the connection structure are optimized.

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