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研究生： 吳建宏
Wu, Chien-Hung
論文名稱： 應用於先進互補式金氧半電晶體具高功函數差與優異熱穩定性之金屬/高介電係數介電層閘極研究
High Temperature Stable Metal Gate/High-k Dielectrics CMOS with Large Work-Function Difference
指導教授： 荊鳳德
Chin, Feng-Der
王水進
Wang, Shui-Jinn
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 93
中文關鍵詞： 高介電係數 、互補式金氧半電晶體 、金屬閘極
外文關鍵詞： metal gate, high-k, CMOSFETs
相關次數： 點閱：95  下載：5 
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    • 隨著CMOS元件尺寸之持續縮微，閘極氧化層厚度亦須隨之降低。傳統SiO2材料應用於奈米元件的主要挑戰，在於超薄閘極SiO2層漏電流之控制，特別是當氧化層小於3 nm時，由於直接穿隧(direct tunneling)機率之增強，將導致閘極電流急遽增加。一旦製程技術進入45 nm領域，所需閘極氧化層等效厚度將小於或等於1.3 nm。顯然，新世代製程若持續使用SiO2，將可能帶來極高閘極漏電流，導致整體CMOS電路失效。於此情況下，高介電係數(high-k)材料乃為發展新世代CMOS製程技術，顯然發展替代氧化矽的高介電係數介電層技術，已是刻不容緩。
    高介電係數材料之使用，除可增加閘極電容有效提昇元件驅動能力外，於相同閘極電容值下，其薄膜厚度(physical thickness)將遠大於氧化層厚度，可大幅降低介電層之電場強度及閘極漏電流[1-3]。另外，金屬閘極也將全面替代多晶矽閘極(Poly-Si)，因為多晶矽閘極本身的缺點，例如有多晶矽閘極空乏、硼離子擴散，還有高阻值的特性。金屬最希望的功函數值，對p型的金氧半電晶體是約5.2電子伏特(eV)，對N型的金氧半電晶體約4.1電子伏特(eV)。至於金屬閘極其優點除了降低電阻值、高溫穩定度佳、提高對閘極電流驅動力之外，更重要的是，可以調整平帶電壓，進一步調整啟動電壓為~0.1V左右。近年來，高介電係數介電層與金屬閘極的技術發展，已成為半導體產業最重要的研究之一。在本論文中，吾人將探討數種高介電係數材料與金屬閘極的研究與應用。
    首先，我們將探討高介電係數氮氧化鋁鉿(HfAlON)介電層，分別選用矽化鐿(YbSix)與矽化銥(IrxSi)所形成的全金屬矽化閘極(FUSI)來當n-型與p-型金氧半場效電晶體的閘極。而氮氧化鋁鉿雖然比氧化鉿有較低的介電係數，但卻有較佳的熱穩定性。另外，使用矽化鐿與矽化銥全金屬矽化閘極比純金屬閘極有更好的熱穩定性，且可有效降低費米栓(Fermi-level pinning)效應所造成的有效功函數偏移現象。結果顯示，氧化鋁鉿結合矽化鐿與矽化銥全金屬矽化閘極，是實現雙金屬閘極互補式金氧半電晶體很好的選擇之一。
    其次，我們將高介電係數氧化矽鉿(HfSiON)應用於低功函數矽化鉿(HfSix)金屬閘極，可以有效降低有效氧化層厚度(EOT)來達成提升電流密度及降低臨界電壓，進而得到大的驅動電流元件特性。此良好的元件特性也通過可靠度分析的檢測，將可應用於未來的CMOS製程。
    最後，我們將探討另一種高介電係數介電層氮氧化鑭鉿(HfLaON)，結合矽化銥閘極(IrxSi)應用於p-型金氧半場效電晶體。氮氧化鑭鉿與氮氧化矽鉿同樣具有良好的高溫熱穩定性，但氮氧化鑭鉿卻有比氮氧化矽鉿還要高的介電係數的優點。此外，矽化銥閘極具可以在1000oC以下穩定，且結合氮氧化鑭鉿介電層後，其有效功函數將可調變到適用於p-型金氧半場效電晶體的應用，特別是我們的製程方式也完全符合現在工業界的技術，預期未來我們的製程材料將為工業界廣泛使用。

    CMOS technology is being continuously scaled down, and gate dielectric thickness is also decreasing. Traditional gate dielectric oxide layer SiO2 will face the physical limitation of nano devices - large gate leakage current. As the thermally grown gate oxide shrink to a thickness blow 3 nm, considerable gate leakage current arising from direct tunneling will inevitably hinder the functionality of the device. As the process technology becomes attractive for the 45 nm node and beyond, the equivalent oxide thickness (EOT) of the gate dielectrics oxide layer will be down to 1.3 nm or even thinner. It is quite obvious that the gate leakage current will be higher and CMOS circuit will fail, using the SiO2 in next process generation. Various insulators with high-permittivity (high-k) have been proposed and investigated to serve as alternative to SiO2 toward CMOS technology of next generation.
    High-κ dielectric materials have been proposed to serve as alternative to SiO2 because they can be made thicker to avoid gate leakage current while still keep the same or even better capability to induce channel change. In addition, traditional poly-Si gate is also going to be replaced by metal gates because poly-Si gate encounters several inherent limitations, such as poly-Si depletion, boron penetration, and high resistivity. On the contrary, the metal gate will be promising with merits of low resistivity, high temperature stable, high current drive, and fitting flatband voltage to tune threshold voltage (Vt=0.1V). Essentially, the preferred work function of the metals are ~5.2 eV for p-MOSFETs and ~4.1 eV for n-MOSFETs. Recently, metal-gate/high-κ process technologies become one of the most important researches in the semiconductor industry. In this dissertation, we will investigate the application of several high-κ dielectric and metal gate process technologies.
    First of all, we will study the application of HfAlON dielectric with YbSix and IrxSi full silicidation (FUSI) metal gates in n-MOSFETs and p-MOSFETs, respectively. Although HfAlON has smaller dielectric constant than HfO2, it has better thermal stability. Besides, using YbSix and IrxSi FUSI metal gates can obtain better thermal stability than using pure metal gates, and also can reduce the effective work function shifts due to Fermi-level pinning effect. Our experimental results indicate that integrating HfAlON with YbSix and IrxSi FUSI metal gates can achieve dual metal gates development in CMOS technology.
    Next, we will study another high-κ dielectric HfSiON with HfSix gate of low work function in n-MOS application. Good device performance was achieved - such as a high drive current and low threshold voltage due to the down-scaling effective oxide thickness (EOT) provided by the high-κ dielectric. In addition, the good performance was achieved reliability certification. It is noted that the proposed HfSix/HfSiON n-MOSFET is full process compatibility with current VLSI lines.
    Finally, the application of high-κ HfLaON dielectric with IrSix gate in p-MOS. HfLaON has good thermal stability (1000oC) as HfSiON, but it has the advantage of higher κ value. Moreover, IrSix also has similarly good thermal stability with the HfLaON dielectric. Integrating HfLaON with IrSix gate will provide the appropriate effective work function in p-MOS application. These data are comparable with or better than the best reported results of high performance metal-gate/high-κ CMOS. The devices are with merit of full process compatible with current VLSI lines.

    Contents Abstract (in Chinese).....................................i Abstract (in English)...................................iii Acknowledgement..........................................vi Contents................................................vii Table Captions...........................................ix Figure Captions...........................................x Chapter 1 Introduction 1.1 Overview of high-k gate dielectrics..............1 1.2 Overview of metal gate electrodes................4 1.3 Innovation and contribution......................5 1.4 Thesis Organization..............................7 References................................................8 Chapter 2 High Work Function IrxSi Gates on HfAlON p-MOSFETs 2.1 Introduction....................................16 2.2 Experimental procedure..........................17 2.3 Results and discussion..........................17 2.4 Conclusion......................................20 References...............................................21 Chapter 3 HfAlON n-MOSFETs Incorporating Low Work Function Gate Using Ytterbium-Silicide 3.1 Introduction....................................31 3.2 Experimental procedure..........................31 3.3 Results and discussion..........................32 3.4 Conclusion......................................34 References...............................................35 Chapter 4 HfSiON n-MOSFETs Using Low Work Function HfSix Gate 4.1 Introduction....................................47 4.2 Experimental procedure..........................48 4.3 Results and discussion..........................49 4.4 Conclusion......................................50 References...............................................52 Chapter 5 High Temperature Stable HfLaON p-MOSFETs with High Work Function Ir3Si Gate 5.1 Introduction....................................62 5.2 Experimental procedure..........................63 5.3 Results and discussion..........................63 5.4 Conclusion......................................66 References...............................................67 Chapter 6 Conclusions and Suggestions for Future Study....85 Vita.....................................................89 Publication Lists........................................90

    Chapter 1
    [1] M. Koyama, K. Suguro, M. Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C. Hongo and A. Nishiyama, “Thermally stable ultra-thin nitrogen incorporated ZrO2 gate dielectric prepared by low temperature oxidation of ZrN,” in IEDM Tech. Dig., pp. 20.3.1-20.3.4, 2001.
    [2] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. -A. Ragnarsson and Rons, “Ultrathin high- gate stacks for advanced CMOS devices,” in IEDM Tech. Dig., pp. 20.1.1-20.1.4, 2001.
    [3] W. Zhu, T. P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson and T. Furukawa, “HfO2 and HfAlO for CMOS: thermal stability and current transport,” in IEDM Tech. Dig., pp. 20.4.1-20.4.4, 2001.
    [4] L. Kang, K. Onishi, Y. Jeon, Byoung Hun Lee, C. Kang, Wen-Jie Qi, R. Nieh, S. Gopalan, R Choi and J. C. Lee, “ MOSFET devices with polysilicon on single-layer HfO2 high- dielectrics,” in IEDM Tech. Dig., pp. 35-38, 2000.
    [5] Rino Choi, Chang Seok Kang, Byoung Hun Lee, K. Onishi, R. Nieh, S. Gopalan, E. Dharmarajan and J. C. Lee, “High-quality ultra-thin HfO2 gate dielectric MOSFETs with TaN electrode and nitridation surface preparation,” in IEDM Tech. Dig., pp. 15-16, 2001.
    [6] Z. J. Luo, T. P. Ma, E. Cartier, M. Copel, T. Tamagawa and B. Halpern, “Ultra-thin ZrO2 (or silicate) with high thermal stability for CMOS gate applications,” in Symp. on VLSI Technology, pp. 135-136, 2001.
    [7] International Technology Roadmap for Semiconductor, 2006.
    [8] J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White Jr, and P. J. Tobin, “Challenges for the integration of metal gate electrodes,” in IEDM Tech. Dig., pp. 287-290, 2004.
    [9] W. P. Maszara, Z. Krivokapic, P. King, J. S. GooIlgweon, and M. R. Lin, “Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates,” in IEDM Tech. Dig., pp.367–370, 2002.
    [10] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack,” in IEDM Tech. Dig., pp. 821-824, 2004.
    [11] H. -J. Cho, C. S. Kang, K. Onishi, S. Gopalan, R. Nieh, R. Choi, E. Dharmarajan and J.C. Lee, “ Novel nitrogen profile engineering for improved TaN/HfO2 Si MOSFET performance,” in IEDM Tech. Dig., pp. 30.2.1-30.2.4, 2001.
    [12] Y. T. Hou, M. F. Li, T. Low, and D. L. Kwong, “ Impact of metal gate work function on gate leakage of MOSFETs,” in DRC Symp., pp. 154-155, 2003.
    [13] Dae-Gyu Park, Kwan-Yong Lim, Heung-Jae Cho, Tae-Ho Cha, Joong-Jung Kim, Jung-Kyu Ko, Ins-Seok Yeo and Jin Won Park, “ Novel damage-free direct metal gate process using atomic layer deposition,” in Symp. on VLSI Technology, pp. 65-66, 2001.
    [14] C. Cabral Jr. , J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy,” Dual workfunction fully silicided metal gates,” in Symp. on VLSI Technology, pp. 184-185, 2004.
    [15] S. B. Samavedam, L. B. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. H. Tseng, P. J. Tobin, D. C. Gilmer, C. Hobbs, W. J. Taylor, J. M. Grant, R. I. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalarn, M. Sadd, B.-Y. Nguyen, and B. White,” Dual-metal gate CMOS with HfO2 gate dielectric,” in IEDM Tech. Dig., pp. 433-436, 2002.
    [16] D. S. Yu, A. Chin, C. C. Laio, C. F. Lee, C. F. Cheng, W. J. Chen, C. Zhu, M.-F. Li, S. P. McAlister, and D. L. Kwong, “3D GOI CMOSFETs with novel IrO2 (Hf) dual gates and high- dielectric on 1P6M-0.18 m-CMOS,” in IEDM Tech. Dig., pp. 181-184, 2004.
    [17] D. S. Yu , A. Chin, C. C. Liao, C. F. Lee, C. F. Cheng, M. F. Li, Won Jong Yoo, and S. P. McAlister, “3D Metal-Gate/High-/GOI CMOSFETs on 1-Poly-6-Metal 0.18-m Si Devices,” IEEE Electron Device Lett. 26, pp. 118-120, Feb. 2005.
    [18] X. P. Wang, C. Shen, Ming-Fu Li, H.Y. Yu, Yiyang Sun, Y. P. Feng, Andy Lim, Hwang Wan Sik, Albert Chin, Y. C. Yeo, Patrick Lo, and D.L. Kwong,” Dual Metal Gates with Band-Edge Work Functions on Novel HfLaO High- Gate Dielectric,” in Symp. on VLSI Technology, pp. 12-13, 2006.
    [19] J. H. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra,” Tunable work function dual metal gate technology for bulk and nonbulk CMOS,” in IEDM Tech. Dig., pp. 359-362, 2002.
    [20] H. Y. Yu, M. F. Li, and D.L. Kwong,” Thermally Robust HfN Metal as a Promising Gate Electrode for Advanced MOS Device Application,” IEEE Transactions on Electron Devices, vol. 51, Apr., 2004.
    [21] H. B. Michaelson, “The work function of the elements and its periodicity,” J. Appl. Phys., vol. 48, pp. 4729-4733, Nov. 1977.
    [22] C. H. Lai, A. Chin, K. C. Chiang, W. J. Yoo, C. F. Cheng, S. P. McAlister, C. C. Chi and P. Wu, “Novel SiO2/AlN/HfAlO/IrO2 memory with fast erase, large Vth and good retention,” in Symp. VLSI Tech. Dig., 2005, pp. 210-211.
    [23] K. C. Chiang, Albert Chin, C. H. Lai, W. J. Chen, C. F. Cheng, B. F. Hung, C. C. Liao, “Very high k and high density TiTaO MIM capacitors for analog and RF applications,” in Symp. VLSI Tech. Dig., 2005, pp. 62-63.
    [24] D. S. Yu, A. Chin, C. H. Wu, M.-F. Li, C. Zhu, S. J. Wang, W. J. Yoo, B. F. Hung and S. P. McAlister, “Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference,” in IEDM Tech. Dig., 2005, pp. 649-652.
    [25] C. H. Huang, D. S. Yu, A. Chin, W. J. Chen, C. X. Zhu, M.-F. Li, B. J. Cho, and D. L. Kwong, “Fully silicided NiSi and germanided NiGe dual gates on SiO2/Si and Al2O3/Ge-On-Insulator MOSFETs,” in IEDM Tech. Dig., 2003, pp. 319-322.
    [26] B. Tavel, T. Skotnicki, G. Pares, N. Carrière, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel, “Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (~2/) without metal CMP nor etching,” in IEDM Tech. Dig., 2001, pp. 815-828.
    [27] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high- gate dielectrics- fermi level pinning controlled PtSix for HfOx(N) pMOSFET,” in IEDM Tech. Dig., 2004, pp.83-86.

    Chapter 2
    [1] J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White Jr, and P. J. Tobin, “Challenges for the integration of metal gate electrodes,” in IEDM Tech. Dig., 2004, pp. 287-290.
    [2] B. Tavel, T. Skotnicki, G. Pares, N. Carrière, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel, “Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (~2/) without metal CMP nor etching,” in IEDM Tech. Dig., 2001, pp. 815-828.
    [3] W. P. Maszara, Z. Krivokapic, P. King, J. S. GooIlgweon, and M. R. Lin, “Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates,” in IEDM Tech. Dig., 2002, pp.367–370.
    [4] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high- gate dielectrics- fermi level pinning controlled PtSix for HfOx(N) pMOSFET,” in IEDM Tech. Dig., 2004, pp.83-86.
    [5] M. Koyama, Y. Kamimuta, T. Ino, A. Kaneko, S. Inumiya, K. Eguchi, M. Takayanagi, and A. Nishiyama, “Careful examination on the asymmetric Vfb shift problem for Poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the Poly-Si interface with small EOT expense,” in IEDM Tech. Dig., 2004, pp. 499-502.
    [6] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack,” in IEDM Tech. Dig., 2004, pp. 821-824.
    [7] K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, “Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices,” in IEDM Tech. Dig., 2004, pp. 91–94.
    [8] C. H. Huang, D. S. Yu, A. Chin, W. J. Chen, C. X. Zhu, M.-F. Li, B. J. Cho, and D. L. Kwong, “Fully Silicided NiSi and germanided NiGe dual gates on SiO2/Si and Al2O3/Ge-On-Insulator MOSFETs,” in IEDM Tech. Dig., 2003, pp. 319-322.
    [9] H. B. Michaelson, “The work function of the elements and its periodicity,” J. Appl. Phys., vol. 48, pp. 4729-4733, Nov. 1977.
    [10] C. C. Liao, C. F. Cheng, D. S. Yu and A. Chin, “The copper contamination effect on Al2O3 gate dielectric on Si,” J. Electrochem. Soc., vol. 151, pp. G693-G696, Oct. 2004.
    [11] Y. H. Lin, F. M. Pan, Y. C. Liao, Y. C. Chen, I. J. Hsieh, and A. Chin, “The Cu contamination effect in oxynitride gate dielectrics,” J. Electrochem. Soc., vol. 148, G627-G629, Nov. 2001.
    [12] A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and reliability of high- Al2O3 gate dielectric with good mobility and low Dit,” in Symp. VLSI Tech. Dig., 1999, pp. 133-134.
    [13] C. H. Huang, M. Y. Yang, A. Chin, W. J. Chen, C. X. Zhu, B. J. Cho, M.-F. Li, and D. L. Kwong, “Very low defects and high performance Ge-On-Insulator p-MOSFETs with Al2O3 gate dielectrics,” in Symp. VLSI Tech. Dig., 2003, pp. 119-120.
    [14] C. H. Lai, A. Chin, K. C. Chiang, W. J. Yoo, C. F. Cheng, S. P. McAlister, C. C. Chi and P. Wu, “Novel SiO2/AlN/HfAlO/IrO2 Memory with Fast Erase, Large Vth and Good Retention,” in Symp. VLSI Tech. Dig., 2005, pp. 210-211.
    [15] K. C. Chiang, Albert Chin, C. H. Lai, W. J. Chen, C. F. Cheng, B. F. Hung, C. C. Liao, “Very high k and high density TiTaO MIM Capacitors for analog and RF applications,” in Symp. VLSI Tech. Dig., 2005, pp. 62-63.

    Chapter 3
    [1] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack,” in IEDM Tech. Dig., 2004, pp. 821-824.
    [2] J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White Jr, and P. J. Tobin, “Challenges for the integration of metal gate electrodes,” in IEDM Tech. Dig., 2004, pp. 287-290.
    [3] B. Tavel, T. Skotnicki, G. Pares, N. Carrière, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel, “Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (~2/) without metal CMP nor etching,” in IEDM Tech. Dig., 2001, pp. 815-828.
    [4] W. P. Maszara, Z. Krivokapic, P. King, J. S. GooIlgweon, and M. R. Lin, “Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates,” in IEDM Tech. Dig., 2002, pp.367–370.
    [5] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high- gate dielectrics- fermi level pinning controlled PtSix for HfOx(N) pMOSFET,” in IEDM Tech. Dig., 2004, pp.83-86.
    [6] C. S. Park, B. J. Cho, L. J. Tang, and D. L. Kwong, “Substituted aluminum metal gate on high- dielectric for low work-function and Fermi-level pinning free,” in IEDM Tech. Dig., 2004, pp. 299 - 302.
    [7] M. Koyama, Y. Kamimuta, T. Ino, A. Kaneko, S. Inumiya, K. Eguchi, M. Takayanagi, and A. Nishiyama, “Careful examination on the asymmetric Vfb shift problem for Poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the Poly-Si interface with small EOT expense,” in IEDM Tech. Dig., 2004, pp. 499-502.
    [8] K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, “Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices,” in IEDM Tech. Dig., 2004, pp. 91-94.
    [9] C. H. Huang, D. S. Yu, A. Chin, W. J. Chen, C. X. Zhu, M.-F. Li, B. J. Cho, and D. L. Kwong, “Fully Silicided NiSi and germanided NiGe dual gates on SiO2/Si and Al2O3/Ge-On-Insulator MOSFETs,” in IEDM Tech. Dig., 2003, pp. 319-322.
    [10] C. Y. Lin, D. S. Yu, A. Chin, C. Zhu, M. F. Li, and D. L. Kwong, “Fully silicided NiSi gate on La2O3 MOSFETs,” IEEE Electron Device Lett. 24, pp. 348-350, May 2003.
    [11] D. S. Yu, K. C. Chiang, C. F. Cheng, A. Chin, C. Zhu, M. F. Li, and D. L. Kwong, “Fully Silicided NiSi:Hf/LaAlO3/Smart-Cut-Ge-On-Insulator n-MOSFETs with high electron mobility” IEEE Electron Device Lett. 25, pp. 559-561, Aug. 2004.
    [12] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier source/drain MOSFET using ytterbium silicide,” IEEE Electron Device Lett. 25, pp. 565-567, Aug. 2004.
    [13] C. C. Liao, C. F. Cheng, D. S. Yu and A. Chin, “The copper contamination effect on Al2O3 gate dielectric on Si,” J. Electrochem. Soc., vol. 151, pp. G693-G696, Oct. 2004.
    [14] Y. H. Lin, F. M. Pan, Y. C. Liao, Y. C. Chen, I. J. Hsieh, and A. Chin, “The Cu contamination effect in oxynitride gate dielectrics,” J. Electrochem. Soc., vol. 148, G627-G629, Nov. 2001.
    [15] A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and reliability of high- Al2O3 gate dielectric with good mobility and low Dit,” in Symp. VLSI Tech. Dig., 1999, pp. 133-134.
    [16] C. H. Huang, M. Y. Yang, A. Chin, W. J. Chen, C. X. Zhu, B. J. Cho, M.-F. Li, and D. L. Kwong, “Very low defects and high performance Ge-On-Insulator p-MOSFETs with Al2O3 gate dielectrics,” in Symp. VLSI Tech. Dig., 2003, pp. 119-120.
    [17] K. S. Chi and L. J. Chen, “Formation of ytterbium silicide on (111) and (001)Si by solid-state reactions,” Mater. Sci. Semicond. Processing, vol. 4, pp. 269–272, 2001.
    [18] T. Hirano, T. Ando, K. Tai, S. Yamaguchi, T. Kato, S. Hiyama, Y. Hagimoto, S. Takesako,N. Yamagishi, K. Watanabe, R. Yamamoto, S. Kanda, S. Terauchi, Y. Tateshita,Y. Tagawa, H. Iwamoto, M. Saito, S. Kadomura and N. Nagashima, “High performance nMOSFET with HfSix/HfO2 gate stack by low temperature process,” in IEDM Tech. Dig., pp. 911-914, 2005.
    [19] M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J. Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda, “Fluorine incorporation into HfSiON dielectric for Vth control and its impact on reliability for Poly-Si gate pFET,” in IEDM Tech. Dig., pp.425-428, 2005.


    Chapter 4

    [1] J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White Jr, and P. J. Tobin, “Challenges for the integration of metal gate electrodes,” in IEDM Tech. Dig., 2004, pp. 287-290.
    [2] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack,” in IEDM Tech. Dig., 2004, pp. 821-824.
    [3] B. Tavel, T. Skotnicki, G. Pares, N. Carrière, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel, “Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (~2/) without metal CMP nor etching,” in IEDM Tech. Dig., 2001, pp. 815-828.
    [4] W. P. Maszara, Z. Krivokapic, P. King, J. S. GooIlgweon, and M. R. Lin, “Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates,” in IEDM Tech. Dig., 2002, pp.367–370.
    [5] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high- gate dielectrics- fermi level pinning controlled PtSix for HfOx(N) pMOSFET,” in IEDM Tech. Dig., 2004, pp.83-86.
    [6] C. S. Park, B. J. Cho, L. J. Tang, and D. L. Kwong, “Substituted aluminum metal gate on high- dielectric for low work-function and Fermi-level pinning free,” in IEDM Tech. Dig., 2004, pp. 299 - 302.
    [7] M. Koyama, Y. Kamimuta, T. Ino, A. Kaneko, S. Inumiya, K. Eguchi, M. Takayanagi, and A. Nishiyama, “Careful examination on the asymmetric Vfb shift problem for Poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the Poly-Si interface with small EOT expense,” in IEDM Tech. Dig., 2004, pp. 499-502.
    [8] K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, “Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices,” in IEDM Tech. Dig., 2004, pp. 91-94.
    [9] C. H. Huang, D. S. Yu, A. Chin, W. J. Chen, C. X. Zhu, M.-F. Li, B. J. Cho, and D. L. Kwong, “Fully Silicided NiSi and germanided NiGe dual gates on SiO2/Si and Al2O3/Ge-On-Insulator MOSFETs,” in IEDM Tech. Dig., 2003, pp. 319-322.
    [10] C. Y. Lin, D. S. Yu, A. Chin, C. Zhu, M. F. Li, and D. L. Kwong, “Fully silicided NiSi gate on La2O3 MOSFETs,” IEEE Electron Device Lett. 24, pp. 348-350, May 2003.
    [11] D. S. Yu, K. C. Chiang, C. F. Cheng, A. Chin, C. Zhu, M. F. Li, and D. L. Kwong, “Fully Silicided NiSi:Hf/LaAlO3/Smart-Cut-Ge-On-Insulator n-MOSFETs with high electron mobility” IEEE Electron Device Lett. 25, pp. 559-561, Aug. 2004.
    [12] C. H. Wu, D. S. Yu, Albert Chin, S. J. Wang, M.-F. Li, C. Zhu, B. F. Hung, and S. P. McAlister, “High work function IrxSi gates on HfAlON p-MOSFETs,” IEEE Electron Device Lett. 27, no. 2, pp. 90-92, 2006.
    [13] A. Veloso, K. G. Anil, L. Witters, S. Brus, S. Kubicek, J.-F. de Marneffe, B. Sijmus, K. Devriendt, A. Lauwers, T. Kauerauf, M. Jurczak, and S. Biesemans, “Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs,” in IEDM Tech. Dig., pp. 855-858, 2004.
    [14] S. J. Rhee, C. S. Kang, C. H. Choi, C. Y. Kang, S. Krishnan, M. Zhang, M. S. Akbar, and J. C. Lee, “Improved electrical and material characteristics of hafnium titanate multi-metal oxide n-MOSFETs with ultra-thin EOT (~8Å) gate dielectric application,” in IEDM Tech. Dig., pp.837-840, 2004.

    Chapter 5
    [1] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack,” in IEDM Tech. Dig., 2004, pp. 821-824.
    [2] X. Yu, M. Yu and C. Zhu, “Advanced HfTaON/SiO2 gate stack with high mobility and low leakage current for low –standby-power application,” IEEE Electron Device Lett. Vol. 27, no. 6, pp. 498-501, 2006.
    [3] S. C. Song, Z. Zhang, C. Huffman, J. H. Sim, S. H. Bae, P. D. Kirsch, P. Majhi, R. Choi, N. Moumen, and B. H. Lee, “Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 5,pp. 979-989, 2006.
    [4] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high- gate dielectrics- fermi level pinning controlled PtSix for HfOx(N) pMOSFET,” in IEDM Tech. Dig., 2004, pp.83-86.
    [5] K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, “Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices,” in IEDM Tech. Dig., 2004, pp. 91-94.
    [6] P. F. Hsu, Y. T. Hou, F. Y. Yen, V. S. Chang, P. S. Lim, C. L. Hung, L.G. Yao, J. C. Jiang, H. J. Lin, J. M. Chiou, K. M. Yin, J. J. Lee, R. L. Hwang, Y. Jin, S. M. Chang, H. J. Tao, S. C. Chen, M. S. Liang, and T. P. Ma, “Advanced dual metal gate MOSFETs with high- dielectric for CMOS application,” in Symp. VLSI Tech. Dig., 2006, pp. 14-15.
    [7] H. Y. Yu, R. Singanamalla, K. Opsomer, E. Augendre, E. Simoen, J.A. Kittl, S. Kubicek, S. Severi, X.P. Shi, S. Brus, C. Zhao, J.F. de Marneffe, S. Locorotondo, D. Shamiryan, M. Van Dal, A. Veloso, A. Lauwers, M.Niwa, K. Maex, K. D. Meyer, P. Absi, M. Jurczak, and S. Biesemans, “Demonstration of Ni Fully GermanoSilicide as a pFET Gate Electrode Candidate on HfSiON,” in IEDM Tech. Dig., 2005, pp.653-656.
    [8] D. S. Yu, Albert Chin, C. H. Wu, M.-F. Li, C. Zhu, S. J. Wang, W. J. Yoo, B. F. Hung and S. P. McAlister, “Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference,” in IEDM Tech. Dig., 2005, pp. 649-652.
    [9] C. H. Wu, D. S. Yu, Albert Chin, S. J. Wang, M.-F. Li, C. Zhu, B. F. Hung, and S. P. McAlister, “High work function IrxSi gates on HfAlON p-MOSFETs,” IEEE Electron Device Lett. 27, no. 2, pp. 90-92, 2006.
    [10] C. H. Wu, B. F. Hung, Albert Chin, S. J. Wang, F. Y. Yen, Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, “HfAlON n-MOSFETs Incorporating Low Work Function Gate Using Ytterbium-Silicide,” in IEEE Electron Device Lett. vol. 27, no. 6, pp. 454-456, June 2006.
    [11] X. P. Wang, C. Shen, M.-F. Li, H. Y. Yu, Y. Sun, Y. P. Feng, A. Lim, H. W. Sik, A. Chin, Y. C. Yeo, P. Lo, and D. L. Kwong, “Dual metal gates with band-edge work functions on novel HfLaO high-κ gate dielectric,” in Symp. VLSI Tech. Dig., 2006, pp. 12-13.
    [12] S. Bhan and K. Schubert, “Constitution of the systems cobalt-germanium, rhodium-silicon, and some related alloys,” International Journal for Materials Research (Zeitschrift fuer Metallkunde), vol. 51, pp. 327-339, 1960.

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