| 研究生: |
簡兆彥 Chien, Chao-Yen |
|---|---|
| 論文名稱: |
基於分層決策樹之封包分類平衡搜尋樹 Building Balanced Search Tree based on Layered Decision Tree for Packet Classification |
| 指導教授: |
張燕光
Chang, Yeim-Kuan |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2012 |
| 畢業學年度: | 100 |
| 語文別: | 英文 |
| 論文頁數: | 75 |
| 中文關鍵詞: | 封包分類 、演算法 、管線化設計 、FPGA 、決策樹 |
| 外文關鍵詞: | Packet Classification, algorithm, Pipelined Architecture, FPGA, Decision tree |
| 相關次數: | 點閱:132 下載:0 |
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封包分類是路由器中的一個重要組件,它有許多應用例如:服務質量(QoS)、安全、監測、分析與網路入新偵測等。在這篇論文中我們提出了一個稱作分層搜尋樹的方法來解決多維的封包分類問題。分層搜尋樹把決策樹的樹節點重新建成一個趨近平衡的搜尋樹,以此改善傳統決策樹的方法。比起傳統的決策樹方法把rule儲存在樹節點的bucket中,分層搜尋樹的任何節點都設有bucket。因此,在搜尋時一旦封包吻合內部節點則可直接搜尋該節點的bucket,而不需要一直走到葉節點。在軟體環境中,實驗結果顯示分層搜尋樹使用較少的記憶體,即使EffiCuts事先用五維歸類來減少rule replication,所得到的記憶體結果也比分層搜尋樹只用前兩維歸類來的多。此外,在讀取記憶體次數的比較中,分層搜尋樹表現的比HyperCuts與EffiCuts來的好。 並且,我們也對分層搜尋樹設計了硬體的搜尋引擎,以管線化設計(pipeline)與平行處理的架構來實作在Xilinx Virtex-5 的FPGA環境中。由於分層搜尋樹需要較少硬體資源的特性,我們的搜尋引擎最大可以支援到ACL、FW與IPC三種的50K rule table。此外,分層搜尋樹也可達到路由器的高link rate (比如: OC-768),在假設每個最小封包大小為40Bytes的封包下分層搜尋樹的搜尋引擎使用中埠的記憶體可得到超過120 Gps的產能。
Packet classification is an important building block of the Internet routers for many network applications, such as Quality of Service (QoS), security, monitoring, analysis, and network intrusion detection (NIDS). In this thesis, we propose a scheme called Layer based Search Tree (LST) to solve multi-field packet classification problem. LST improves the traditional decision tree based schemes (e.g. HyperCuts and EffiCuts) by reconstructing the leaf nodes of the decision tree as an approximately balanced search tree. Since all the address subspace covered by each node of LST is disjoint, the buckets of the leaf and internal nodes in LST must not be empty. Thus, only the rules in one bucket can match the header values of the incoming packet. Searches on LST are completed immediately after the packet matches a rule in some internal node. In software environment, the experimental results show that LST requires less memory storage even if LST categorizes the rules by two fields to reduce rule duplication rather than five fields in EffiCuts. Besides, LST needs less number of memory accesses than HyperCuts and EffiCuts. In addition, we design the hardware search engine with pipeline and parallel architecture for the LST in Xilinx Virtex-5 FPGA environment. Because the memory usage of LST is very efficient, our search engine can support the ACL, FW, and IPC tables of 50k rules. LST search engine with dual ported memory can sustain the throughput of over 120 Gbps for the packets of minimum size (40 bytes).
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校內:2017-08-31公開