本論文主要研究使用互補式金氧半電晶體製程製作之關鍵射頻元件，以應用於直接降頻接收機與多相位本地振盪器。本論文分成四大部份。第一部份，一個寬頻分散式混頻器使用疊接互補式開關對來改善埠對埠隔離度，同時將其設計成四級分散式架構以實現寬頻及低轉換損耗。所量測之頻寬為5−45 GHz，且LO埠對RF埠之隔離度為33−47 dB、LO埠對IF埠之隔離度為28−53 dB、RF埠對IF埠之隔離度為32−48 dB。第二部份發表一個由電流模式邏輯電路之環形振盪器與兩個三倍頻器所構成之低功耗正交本地振盪器。電流模式邏輯電路之環形振盪器產生正交基頻訊號與差動二倍頻訊號，並且趨動下一級之兩個單平衡混頻器，使頻率可以被提升三倍，同時又能獲得正交輸出與低功耗等優點。當消耗8.7 mW直流功率，可實現16.56−19.8 GHz之頻率可調範圍。第三部份提出一個三模除頻器，它使用三組開關嵌入到再生除頻器之訊號迴路中去產生除二、除三以及除四的功能，除頻器操作在這些模式下所對應之等效模型也被用來說明其工作原理。當操作在除二、除三及除四三種模式下，電路之鎖頻範圍分別為16−23.8 GHz、12.3−18 GHz以及16.8−22.8 GHz。論文的最後一部份則設計三種再生式除頻器。第一種再生式除頻器使用變壓器耦合技術以及源級注入電流模式邏輯電路除頻器來改善迴路除頻器之輸入靈敏度與操作範圍，此外，使用底部本地振盪驅動級之次諧波混頻器也被用來最佳化其轉換增益。該除頻器展示其鎖頻範圍為20.1−24.8 GHz以及6.8 mW之直流功耗。第二種再生除頻器發表一個除三與一個除五除頻器，這兩個除頻器藉由使用除二及除四之正交注入電流模式邏輯電路迴路除頻器去增加鎖頻範圍，同時可實現正交輸入與正交輸出之特性。該除三與除五再生式除頻器經驗證可獲得超寬之鎖頻範圍，分別為9−14.7 GHz 以及7.2−19 GHz。最後，第三種除頻器則介紹了除三、除四以及除八之再生式除頻器，這三個除頻器皆使用電流模式邏輯電路迴路除頻器來增加它們的鎖頻範圍以及使用主動平衡式混頻器(雙平衡吉爾伯混頻器、使用底部本地振盪驅動級之二次諧波混頻器以及四次諧波混頻器)去獲得良好的轉換增益。另外，除二電流模式邏輯電路迴路除頻器之理論鎖頻範圍被分析，基於兩級電流模式邏輯電路架構之除四、八相位迴路除頻器也被設計。經量測結果得知，所製造的除四、八相位電流模式邏輯電路除頻器以及除三、除四與除八之再生式除頻器，其鎖頻範圍分別為1−8 GHz、6.3−10.5 GHz、13.2−18.4 GHz、以及16.8−26 GHz.。

This dissertation investigates the critical RF components fabricated by a standard CMOS process for application into the direct-conversion receiver and the multi-phase local oscillator (LO). There are four parts in this dissertation. In the first part, a broadband distributed mixer uses a cascoded complementary switching pair to improve port-to-port isolation and forms a four-stage distributed topology to achieve a broad bandwidth and reduce conversion loss (CL). The measured operation bandwidth was from 5−45 GHz, and the LO-to-RF, LO-to-IF, and RF-to-IF isolations were from 33−47 dB, 28−53 dB, and 32−48 dB, respectively. The second part presents a low-power quadrature LO, which is composed of a current-mode-logic (CML) ring oscillator integrated with two frequency triplers. The CML ring oscillator generates the quadrature signals and the frequency-doubled signals to drive two single-balanced mixers for up-converting the frequency by triple and achieving quadrature outputs and low power consumption. When consuming 8.7 mW of direct-current (DC) power, the frequency tuning range of 16.56−19.8 GHz was achieved. The third part proposes a triple-modulus FD which uses three pairs of switches inserted in the signal paths of the regenerative divider to provide three selectable division ratios of 1/2, 1/3, and 1/4. The corresponding behavior models of the divider in these modes are also utilized to explain the operation principle. Operated at 1/2, 1/3, and 1/4 dividing modes, the circuit obtained the locking ranges of 16−23.8 GHz, 12.3−18 GHz, and 16.8−22.8 GHz. The last part designs three kinds of RFDs. The first-case RFD uses a transformer-coupling technique and a source-injected current-mode-logic (S-CML) FD to improve the input sensitivity and the operation range of the loop divider. A subharmonic mixer (SHM) with bottom LO was used to optimize the conversion gain. The divider exhibited a locking range of 20.1−24.8 GHz with a 6.8 mW of power consumption. The second-case RFD presents a ÷3 and ÷5 RFDs by using a ÷2 and ÷4 quadrature-injected CML loop dividers to widen their locking ranges and achieve quadrature inputs and quadrature outputs. The ÷3 and the ÷5 dividers were demonstrated with the ultra-wide locking ranges of 9−14.7 GHz and 7.2−19 GHz, respectively. Finally, the third case introduces three RFDs with a division ratio of 3, 4, and 8, respectively. These RFDs use CML loop dividers to widen their locking ranges and active balanced mixers (i.e., double-balanced Gilbert mixer, and the 2× and 4× SHMs with bottom LO) to obtain good conversion gain. In addition, the theoretical locking range of the ÷2 CML loop divider is analyzed and a ÷4 octet loop divider based on a two-stage CML divider is designed. Measured results showed that the fabricated ÷4 octet CML FD and ÷3, ÷4, and ÷8 RFDs obtained the locking ranges of 1−8 GHz, 6.3−10.5 GHz, 13.2−18.4 GHz, and 16.8−26 GHz, respectively.

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