中值濾波器已被廣泛使用在許多領域，在數位訊號處理和影像處理領域中，就常被使用來去除訊號和影像中的雜訊。中值濾波器的硬體實現在一些即時的應用中占有極為重要的角色。
本論文提出了一低功率一維中值濾波器架構。在此架構中實現兩種降低功率消耗的技術。首先是提出一低功率FIFO，以降低動態功率消耗，這是透過減少電路中的訊號傳遞達到的。為了再減少更多的功率消耗，Clock gating亦被實現在我們的架構中。因為有很高比例的暫存器的值會經常維持不變，特別是一些大儲存窗口的中值濾波器，所以關閉這些暫存器也可以大幅減少動態功率消耗。
本論文中所有架構都是由Verilog HDL實現，並由Synopsys Design Compiler使用TSMC 90nm的標準元件庫做合成。實驗結果顯示，本論文提出的架構不只運算速度和面積成本與現有技術的效果相當，更可有效減少功率消耗。

Median filter is widely used in digital signal processing and image processing to filter out the noises in signals and images. The hardware implementation of median filter plays an important role in some real-time applications.
A low-power architecture of one-dimensional median filter is proposed in this dissertation. Two techniques are implemented in the proposed architecture to reduce power consumption. First of all, a low-power FIFO is proposed for dynamic power reducing. The low-power FIFO reduces the power consumption by minimizing the switching activities. To further reduce power consumption, the clock gating technique is also implemented in the circuit. A high proportion of registers will preserve its original value at each clock cycle, especially for large window size median filters. Thus, turning off these registers can also reduce a lot of power consumption.
The architectures in this dissertation were implemented by the Verilog HDL, and synthesized by Synopsys Design Compiler with the TSMC 90nm standard cell library. The experimental results show that the proposed architecture can reduce power consumption as well as achieve nearly the same operating speed and area cost, compared with the state-of-art techniques.

[1] S. A. Fahmy, P. Y. K. Cheung, and W. Luk, “High-throughput one-dimensional median and weighted median filters on FPGA,” IET Computers & Digital Techniques, vol. 3, no. 4, pp. 384–394, Jul. 2009.
[2] V. G. Moshnyaga and K. Hashimoto, “An efficient implementation of 1-D median filter,” in Proc. 52nd IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS), 2009, pp. 451–454.
[3] R.-D. Chen, P.-Y. Chen, and C.-H. Yeh, “Design of an area-efficient one-dimensional median filter” , IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 662–666, Oct. 2013.
[4] R.-D. Chen, P.-Y. Chen, and C.-H. Yeh, “A low-power architecture for the design of a one-dimensional median filter,” IEEE Trans. Circuits and Systems II: Express Briefs, 2014.
[5] Eesa Nikahd, Payman Behnam, and Reza Sameni, “High-Speed Hardware Implementation of Fixed and Runtime Variable Window Length 1-D Median Filters” IEEE Trans. Circuits and Systems II: Express Briefs, 2016.
[6] C.-Y. Lee, P.-W. Hsieh, and J.-M. Tsai, “High-speed median filter designs using shiftable content-addressable memory,” IEEE Trans. Circuits and Systems for Video Technology, vol. 4, no. 6, pp. 544–549, Dec. 1994.
[7] V. V. R. Teja, K. C. Ray, I. Chakrabarti, and A. S. Dhar, “High throughput VLSI architecture for one dimensional median filter,” in Proc. IEEE Int. Conf. Signal Processing, Communications and Networking (ICSCN), 2008, pp. 339–344.
[8] Z. Vasicek and L. Sekanina, “Novel hardware implementation of adaptive median filters,” in Proc. 11th IEEE Workshop Design and Diagnostics of Electronic Circuits and Systems(DDECS), 2008, pp. 1–6.
[9] C.-T. Chen, L.-G. Chen, and J.-H. Hsiao, “VLSI implementation of a selective median filter,” IEEE Trans. Consumer Electronics, vol. 42, no. 1, pp. 33–42, Feb. 1996.
[10] J. Cadenas, G. M. Megson, R. S. Sherratt, and P. Huerta, “Fast median calculation method,” Electron Letters, vol. 48, no. 10, pp. 558–560, May 2012.
[11] C. Choo and P. Verma, “A real-time bit-serial rank filter implementation using Xilinx FPGA,” in Proc. SPIE, vol. 6811, Real-Time Image Processing, 2008, pp. 68 110F-1–68 110F-8.
[12] M. Karaman, L. Onural, and A. Atalar, “Design and implementation of a general-purpose median filter unit in CMOS VLSI,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 505–513, Apr. 1990.
[13] D. Prokin and M. Prokin, “Low hardware complexity pipelined rank filter,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 57, no. 6, pp. 446–450, Jun. 2010.
[14] Design Compiler User Guide, Version C-2009.06, June 2009
[15] K. J. R. Liu, An-Yeu Wu, A. Raghupathy, J. Chen, “Algorithm-based low-power and high-performance multimedia signal processing”, Proceedings of the IEEE, vol.86, Jun. 1998.
[16] “Low-Power CMOS VLSI circuit design”, by Kaushik Roy and Sharat C. Prasad, John Wiley & Sons, INC, 2000.
[17] Power Compiler User Guide, Version D-2010.03-SP2, June 2010
[18] Jitesh Shinde, S. S. Salankar, “Clock gating — A power optimizing technique for VLSI circuits”, Annual IEEE India Conference, 2011