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研究生：	王前偉 Wang, Chien-Wei
論文名稱：	鐵電層負電容場效電晶體模型建立與模擬分析 Compact Modeling and Simulation of Negative Capacitance FET
指導教授：	盧達生 Lu, Darsen
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2018
畢業學年度：	106
語文別：	英文
論文頁數：	68
中文關鍵詞：	負電容、鐵電材料、負電容場效電晶體
外文關鍵詞：	negative capacitance, ferroelectric material, NCFET
相關次數：	點閱：84 下載：8
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近年來隨著技術的進步，半導體產業遵守著Moore’s Law的規範，穩定的在每12~18個月增加一倍的電晶體數目在矽晶片上，但隨著電晶體數目的增加，技術節點不斷降低，將面臨元件物理極限與功耗的問題。然而鐵電層負電容場效電晶體(NCFET)為目前可行的解決辦法之一，此元件結構可突破次臨界擺幅理論限制(常溫大於或小於60毫伏)並且達到低功耗，本篇研究旨在透過利用HPSICE模擬鐵電層負電容元件暫態分析與實驗數據比較並建立一簡易的物理模型，進一步將此模型實際應用在電晶體模型(BISM 6)上並模擬分析其電特性表現。
為了建立鐵電層負電容元件簡易物理模型，模擬中運用一簡易電路由一外加電阻及鐵電電容組成，其材料參數基於Laudau-Khalatnikov方程式中所得，並萃取自實際量測之極化率與電場關係圖，此處所用之材料為鋯鈦酸鉛(PZT)。因此將可以透過上述之模擬環境建立一簡易物理模型描述PZT電容與端電壓之電壓相依性。
透過模型模擬結果與實驗數據比較，將可進一步探討導致PZT電容有著電壓相依性之成因與機制，因此得知在PZT電容隨外加電壓變化上，中心晶格與鄰近晶格的交互作用力強弱將會與外加電壓交互影響，並且作用力之強弱為外加電壓的函數。
利用上述作為基礎所建立之鐵電層負電容物理模型，將之使用在NCFET上之模擬，可發現在其電性例如次臨界擺幅、電流大小比起未使用鐵電材料均有顯著的改善，此外因製程上因素，P型與N型MOSFET本身之電容值不同，進而影響與鐵電材料電容之匹配問題，最後導致P型次臨界擺幅可達到60 mV/decade以下，而N型無法。

Although the semiconductor ICs abides by Moore’s law in recent years, the development trends show that it will be breached soon. The number of transistors on wafers increases exponentially every year. With the increase of the number of transistors the scaling down of devices elevates the issue of physical limitation of devices and power consumption. The negative capacitance FET (NCFET) can be one of the possible solutions to alleviate this problem. NCFET would not shows the capability of breaking the fundamental limit of subthreshold wing given by 60mV/decade. This is also able to achieve high performance and consumes low power. In this work, I have used HSpice to construct the compact model of the ferroelectric capacitor. The simulation result was compared with the experimental data of transient response of ferroelectric capacitors, which shows a good correspondence between the model and the device. In addition, this model was applied on MOSFET and the characteristics were also analyzed.
A simple series network consisting of an external series resistor and a ferroelectric capacitor has been constructed, to obtain and analyze the transient response of ferroelectric capacitors. We have described the dependencies between voltages and ferroelectric capacitors in this model and have discussed the mechanism, that leads to such phenomena. By calibration of the model with experimental data proves the legitimacy of this model. Finally, it has been concluded, that the strength of interaction between adjacent domains is a function of the input voltage.
According to the simulation on this model, we found the issues such as subthreshold swing and drain current both get improved. As, NMOS and PMOS demonstrate different capacitance because they are subjected to different process technology. This causes mismatch between the semiconductor and dielectric capacitances in NMOS, engendering different effects on amplification and subthreshold swing between NMOS and PMOS. As a result of this, the subthreshold swing of PMOS achieved a value less than 60 mV/decade, while NMOS could not.

摘要	i
Abstract	iii
Ackowledgrment	v
Contents	vi
List of figures	viii
List of tables	xii
Chapter 1 Introduction	1
    1-1 Overview	1
1-2 Device	3
Reference	9
Chapter 2 Ferroelectric material	10
2-1 Crystal structure	10
2-2 Basic properties	12
2-3 Measurement	14
2-4 Landau-Khalatnikov theory	16
Reference	19
Chapter 3 Results and discussion	21
    3-1 Measurement of ferroelectric capacitor	21
3-1-1 Sample structure	21
3-1-2 Measurement setup	22
3-1-3 Measurement result	23
3-2 PZT capacitor simulation	32
3-2-1 Device modeling, simulation method, measurement and fabrication	32
3-2-2 Mechanism discussion and simulation result	36
3-3 PVDF capacitor simulation	43
3-4 NCFET simulation	47
3-5 Questions	55
Reference	58
Chapter 4 Conclusion	61
Appendix	63
A. Detailed code for 3-2 PZT capacitor simulation	63
B. Detailed code for 3-3 PVDF capacitor simulation	66

Figure 1.1 The apply voltage versus technology node.	2
Figure 1.2 The reason why we reduce power consumption by NCFET.	3
Figure 1.3 Energy landscapes of ferroelectric (left) and ordinary insulators (right).	4
Figure 1.4 Energy landscape description of ferroelectric negative capacitance applied external electric field.	6
Figure 1.5 A ordinary capacitor with ferroelectric capacitor let ferroelectric material stay at negative capacitance state.	8
Figure 1.6 The scheme of MOSFET with ferroelectric layer. Cins is represents the capacitance of ferroelectric layer. Cs is the capacitance including the semiconductor capacitance and the ordinary insulator layer.	8
Figure 2.1 The crystal structure of PTO.	10
Figure. 2.2 The out-of-plane PFM snapshots for the 40 nm film (PZT). It is on the same 2 μm x 2 μm area after subsequently increasing negative DC voltages are applied.	11
Figure 2.3 The characteristic of ferroelectric material.	12
Figure 2.4 Characteristic of most materials.	13
Figure 2.5 The hysteresis of ferroelectric materials.	13
Figure 2.6 The measurement setup for ferroelectric capacitor.	14
Figure 2.7 The test circuit for single domain and multiple domain of simulation. [8]	18
Figure 2.8 It shows the simulation result between single domain and multiple domain. (PZT capacitor )[9]	18
Figure 3.1 Each sample have four-pin TO-18 transistor-type header. It matches to the socket board for measurement.	22
Figure 3.2 The structure of the PZT capacitor.	22
Figure 3.3 The socket board we used in the measurement.	23
Figure 3.4 The schematic of the resistor-ferroelectric capacitor circuit for observing the transient response of ferroelectric capacitors.	23
Figure 3.5 The hysteresis of type AB PZT capacitor.	24
Figure 3.6 The normalized C-V curve. The switching voltage of type AB PZT capacitor are about 2V and -1.5V. The frequency is 500Hz and the waveform is triangular wave.	25
Figure 3.7 When the amplitude of the input voltage is 9V, there are obvious difference between the PZT capacitor and the ordinary capacitor.	27
Figure 3.8 When the amplitude of the input voltage is 1V, there are not any difference. Green line is PZT capacitor, yellow line is ordinary capacitor.	27
Figure 3.9 Each figure is different external resistor. They are 200kΩ, 309kΩ and 402kΩ, respectively.	28
Figure 3.10 Each figure is different frequency of the input voltage. They are 500Hz, 700Hz and 1000Hz, respectively.	29
Figure 3.11 The hysteresis of different frequency of the input voltage. Black line is 500Hz, red line is 700Hz and blue line is 1000Hz.	30
Figure 3.12 The voltage dependence of hysteresis. The black line is 9V, the red line is 6V, the blue line is 3V and the green line is 1V.	31
Figure 3.12 (a) The schematic of the resistor-ferroelectric capacitor circuit for observing the transient response of ferroelectric capacitors. Vin, Vout are the input and output voltages, respectively, Rseries is the external resistor, and CFE is the ferroelectric capacitor. (b) Equivalent circuit representing the multiple domain Landau-Khalatnikov model for the ferroelectric capacitor including independent parameters for each of the capacitors: Rrho is the internal resistance, Vinter is a dependent voltage source, CFE1, CFE2 and CFE3 are single-domain ferroelectric capacitors.	33
Figure 3.13 The transient response of PZT capacitor. Each different input voltage uses different parameter interaction factor kin. The frequency is 1 kHZ.	37
Figure 3.14 The transient response of PZT capacitor. In this simulation, we do not include Rrho in the model.	40
Figure 3.15. The transient response of PZT capacitor. Here the interaction factor kin is a function of P. The simulation setup is the same between fig. 3.14 and fig. 3.15.	42
Figure 3.17 (left) Experiment data from UOS (right) Hspice Simulation (10V)	45
Figure 3.18 (left) Experiment data from UOS (right) Hspice Simulation (9V)	45
Figure 3.19 (left) Experiment data from UOS (right) Hspice Simulation (7V)	45
Figure 3.20 (left) Experiment data from UOS (right) Hspice Simulation (5V)	46
Figure 3.21 (left) Experiment data from UOS (right) Hspice Simulation (3V)	46
Figure 3.22 The diagram structure of NCFET.	47
Figure 3.23 The transient response of top gate and internal gate for NMOS when the thickness of ferroelectric layer is 5, 10, 15 nm.	49
Figure 3.24 (right) Id-Vg curve of NCFET correspond to previous condition.	49
Figure 3.25 The transient response of top gate and internal gate for PMOS when the thickness of ferroelectric layer is 5, 10, 15 nm.	50
Figure 3.26 Id-Vg curve of NCFET correspond to previous condition.	50
Figure 3.27 Id-Vg curve of the top gate and the internal gate.	52
Figure 3.28 Figure 3.6 Id-Vg curve of the top gate and the internal gate.	52
Figure 3.29 C-V curve of n type MOSFET and p type MOSFET.	54
Figure A1 va code of ferroelectric capacitor for single domain.	63
Figure A2 va code of ferroelectric capacitor for multiple domain and voltage dependence.	64
Figure A3 sp code of test circuit for transient response of ferroelectric capacitor.	65
Figure B1 va code of ferroelectric capacitor for single domain.	66
Figure B2 sp code of test circuit and multiple domain.	67
Figure B3 Matlab code for generating 50 ferroelectric capacitors. Each of the three Landau parameters α, β, and γ are randomly generated from a Gaussian distribution	68
Figure B4 Matlab code for generating 50 sub-circuit of ferroelectric capacitor.	68

Table. 3.1. Parameter adopted for HSpice simulation. α, β, and γ are Gaussian-distributed with standard deviations σ and mean values μ. The mean values for α and β were extracted from measured polarization-voltage characteristics. The internal resistance ρ is kept constant.	37
Table. 3.2 Gaussian distribution parameters used for simulation results shown in Fig. 3.16. The mean values we used(alpha0 and beta) are the parameters extracted by UOS.	43
Table 3.3 The subthreshold swing of top gate and internal gate from fig. 3.27 and fig. 3.28.	51
                                    

Chapter 1
[1] M. H. Lee, S. T. Fan, C. H. Tang, P. G. Chen, Y. C. Chou, H. H. Chen, et al., "Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 12.1.1-12.1.4.
[2] S. Salahuddin, "Negative capacitance in a ferroelectric-dielectric heterostructure for ultra low-power computing," p. 846111.
[3] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, et al., "Negative capacitance in a ferroelectric capacitor," Nat Mater, vol. 14, pp. 182-6, Feb 2015.
Chapter 2
[1] A. I. Khan, "Negative capacitance for ultra-low power computing," Ph.D. dissertation, Dept. Engineering-electrical engineering and computer sciences,Univ. of California, Berkeley,USA , 2015.
2-2
[2] http://www.materialsciencejournal.org/vol11no2/crfe2o4-bifeo3-perovskite-multiferroic-nanocomposites-a-review/
[3] https://en.wikipedia.org/wiki/Ferroelectricity
2-3
[4] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, et al., "Negative capacitance in a ferroelectric capacitor," Nat Mater, vol. 14, pp. 182-6, Feb 2015.
2-4
[5] S. Salahuddin, "Negative capacitance in a ferroelectric-dielectric heterostructure for ultra low-power computing," p. 846111.
[6] L. D. landau and I. M. Khalatnikov, “On the anomalous absorption of sound near a second order phase transition point”, Dok. Akad. Nauk, SSSR, vol. 96, pp 469-472, Jun, 1954.
[7] V. V. Lo, “Simulation of thickness effect in thin ferroelectric films using Landau-Khalatnikov theory”, Journal of Applied Physics, Vol.93, No. 5, pg. 3353-3359, 2003.
[8] M. Hoffmann, M. Pešić, K. Chatterjee, I. Khan Asif, S. Salahuddin, S. Slesazeck,U. Scheorder, T. Mikolajick, "Direct Observation of Negative Capacitance in Polycrystalline Ferroelectric HfO2," Advanced Functional Materials, vol. 26, pp. 8643-8649, Dec. 2016
[9] Z. C. Yuan, S. Rizwan, M. Wong, K. Holland, S. Anderson, T. B. Hook, D. Kienle, S. Gadelrab, P. S. Gudem, M. Vaidyanathan, "Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs," IEEE Transactions on Electron Devices, vol. 63, pp. 4046-4052, Sep. 2016
[10] A. I. Khan, "Negative capacitance for ultra-low power computing," Ph.D. dissertation, Dept. Engineering-electrical engineering and computer sciences,Univ. of California, Berkeley,USA , 2015.
Chapter 3
[1] The datasheet about type AB PZT ferroelectric capacitor from Radiant Technology, Inc.
[8] Z. C. Yuan, S. Rizwan, M. Wong, K. Holland, S. Anderson, T. B. Hook, et al., "Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs," IEEE Transactions on Electron Devices, vol. 63, pp. 4046-4052, 2016.
3-2
[2] S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, pp. 405-410, Feb. 2008.
[3] J. Jo and C. Shin, “Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching,” IEEE Electron Device Letters, vol. 37, no. 3, Jan. 2016, pp. 245-248
[4] M. H. Lee, S. T. Fan, C. H. Tang, P. G. Chen, Y. C. Chou, H. H. Chen, et al., "Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 12.1.1-12.1.4.
[5] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, et al., "Negative capacitance in a ferroelectric capacitor," Nat Mater, vol. 14, pp. 182-6, Feb 2015.
[6] H. Ku and C. Shin, "Transient Response of Negative Capacitance in P(VDF_0.75-TrFE_0.25) Organic Ferroelectric Capacitor," IEEE Journal of the Electron Devices Society, vol. 5, pp. 232-236, 2017.
[7] M. Kobayashi, N. Ueyama, K. Jang, and T. Hiramoto, "Experimental study on polarization-limited operation speed of negative capacitance FET with ferroelectric HfO_2," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 12.3.1-12.3.4.
[8] Z. C. Yuan, S. Rizwan, M. Wong, K. Holland, S. Anderson, T. B. Hook, et al., "Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs," IEEE Transactions on Electron Devices, vol. 63, pp. 4046-4052, 2016.
[9] S.-C. Chang, U. E. Avci, D. E. Nikonov, S. Manipatruni, and I. A. Young, "Physical Origin of Transient Negative Capacitance in a Ferroelectric Capacitor," Physical Review Applied, vol. 9, p. 014010, Jan. 2018.
[10] M. Hoffmann, M. Pešić, K. Chatterjee, I. Khan Asif, S. Salahuddin, S. Slesazeck, et al., "Direct Observation of Negative Capacitance in Polycrystalline Ferroelectric HfO2," Advanced Functional Materials, vol. 26, pp. 8643-8649, Dec. 2016.
[11] M. Hoffmann, A. I. Khan, C. Serrao, Z. Lu, S. Salahuddin, M. Pešić, et al., "Ferroelectric negative capacitance domain dynamics," Journal of Applied Physics, vol. 123, p. 184101, 2018.
[12] A. I. Khan, "Negative capacitance for ultra-low power computing," Ph.D. dissertation, Dept. Engineering-electrical engineering and computer sciences,Univ. of California, Berkeley,USA , 2015.
[13] HSpice User Manual, Synopsys Inc., 2016
3-3
[8] Z. C. Yuan, S. Rizwan, M. Wong, K. Holland, S. Anderson, T. B. Hook, et al., "Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs," IEEE Transactions on Electron Devices, vol. 63, pp. 4046-4052, 2016.
3-4
[14] BSIM6 User Manual, University of California, Berkeley, 2015
[15] A Verilog-A Compact Model for Negative Capacitance FET manual, Purdue University, 2016
[16] M. H. Lee, Y. T. Wei, K. Y. Chu, J. J. Huang, C. W. Chen, C. C. Cheng, et al., "Steep slope and near non-hysteresis of FETs with antiferroelectric-like HfZrO for low-power electronics," IEEE Electron Device Letters, vol. 36, pp. 294-296, 2015.
[17] MVSNC model user manual, MIT, Georgia Tech and U. C. Berkeley

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