高漏電流功耗 (leakage power) 在現代IC設計當中已變成一個很嚴重的問題。藉由把暫時不會使用之電路區塊的電源阻斷掉，電源閘控式設計 (power gating) 已成為減少漏電流功耗的最有效方法之一。在電路被喚醒的過程中，同時將睡眠電晶體 (sleep transistor) 一起打開將產生額外的湧浪電流 (surge current)，這些湧浪電流可能會威脅到電路訊號的完整性。為了避免在喚醒電路的過程中產生巨大的湧浪電流，睡眠電晶體的喚醒順序 (wake-up sequence) 應該要被小心地設計。另一方面，PMOS型的睡眠電晶體可能會因負偏壓溫度不穩定效應 (NBTI) 的影響而受害，因為它的喚醒時間 (wake-up time) 可能會隨著電路老化變長。而傳統喚醒順序固定式的方法在設計時並沒有考量到NBTI效應的影響，這將導致在電路老化後它們的喚醒時間將變得更長，甚至長到無法接受的程度。所以在這篇論文中，我們提出一個全新的、能夠感知NBTI效應的喚醒策略 (NBTI-aware wake-up strategy) 來減少喚醒時間。我們的策略首先會根據不同的電路老化狀態找出若干組適當的喚醒順序，然後再根據電路真實的老化程度 (也就是經過數月或數年的老化時間後) 在電路運行時動態地改變喚醒順序。實驗結果顯示，和傳統喚醒順序固定式的方法相比較，我們的策略最多可減少平均喚醒時間 (average wake-up time ) 達45.04%。同時依據我們的估算，為了實現可變喚醒順序的電路結構所產生的額外面積，最多不會超過整體電路面積的6%。

High leakage power consumption has become a serious problem in modern IC design. By isolating a block of circuit which is not in use from power supply, power gating has become one of the most effective ways to reduce leakage power. During circuit wake-up process, turning on sleep transistors simultaneously may induce excessive surge current, which will threaten signal integrity. To avoid significant surge current, sleep transistor wake-up sequence should be carefully designed. On the other hand, PMOS sleep transistors may suffer from Negative-Bias Temperature Instability (NBTI), and the wake-up time is increased after circuit aging. Conventional fixed wake-up sequence based methods does not consider the NBTI effect, which may result in longer or unacceptable wake-up time after circuit aging. Therefore, in this thesis, we propose a novel NBTI-aware wake-up strategy to reduce the wake-up time. Our strategy first finds a set of proper wake-up sequences under different aging circumstance and then dynamically reconfigures wake-up sequences at runtime based on the actual aging scenario (i.e. different months or years of aging). Experimental results show that compared with a traditional fixed wake-up sequence approach, our strategy can reduce up to 45.04% average wake-up time latency. Meantime, according to our estimation, to implement the reconfigurable wake-up sequence structure, the parasitic area overhead is no more than 6% total circuit area.

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