隨著微影製程技術的進步，摩爾定律逐漸達到物理限制並開始遇到瓶頸，進而導致半導體產業開始追求"More than Moore"的策略。這種策略不再僅是追求縮小電晶體尺寸，開始開發許多新的材料與技術。本研究旨在探討低溫下半導體元件的應用，考慮到在低溫條件下，MOSFET 具有較高的電子遷移率和更陡峭的次臨界擺幅。
此外，低溫條件下的應用也相當廣泛，包括高性能計算和量子計算。然而，在這些新型應用中，由於MOSFET 的功耗造成的過多熱量，已經成為互補式金氧半電晶體（CMOS）運作的主要挑戰之一。雖然降低溫度似乎有利於縮小供應電壓 VDD 和降低功耗，但 VDD 和 T 之間的相關性如何影響裝置性能和功耗效率，目前仍不完全清楚。
在此篇研究中，我們提出了一項全面的研究，針對在從 300 到 10 K 的溫度範圍內，對不同 VDD下的 MOSFET 進行了功率性能的評估。我們發現由於次臨界擺幅的飽和現象，限制了 VDD 的進一步縮放。然而，我們也發現在T ≦ 100 K 的條件下，且在不同技術節點之間，分別存在著最適合的 VDD(T) 並能有效提高元件的功耗效率，從而在低溫條件下改善裝置的性能。為了進一步深化我們的理解，我們建立了一個擬合模型來萃取能帶尾參數。這個模型使我們能夠在不同的技術節點下進行深入的分析，並從結果發現了高斯分布的接面能態會隨著溫度變化。以上這些結果對於未來低溫應用的設計與優化，將提供重要的參考和指引。

With the advancement of photolithography process technology , the physical limitations have gradually made Moore's Law reach a bottleneck, leading the semiconductor industry to begin pursuing a "More than Moore" strategy. This strategy goes beyond merely minimizing transistor dimensions and includes the development of numerous new materials and technologies. The aim of this study is to investigate the application of semiconductor components at low temperatures, considering that MOSFETs exhibit higher electron mobility and steeper subthreshold swing under l ow temperature conditions.
Additionally, there are a wide range of applications for low temperature operations,including High Performance Computing (HPC) and Quantum Computing (QC). However, in these novel applications, the undesired heat produced by the power consumption of MOSFET s has become one of the main challenges for the operation of Complementary Metal Oxide Semiconductor (CMOS). Although reducing the temperature (T) seems beneficial for supply voltage (???) scaling and power reduction, the relationships between ??? and T and how they affect device performance and power consumption remain unclear.
In this study, we present a comprehensive investigation focusing on the power performance evaluation of MOSFETs under different ? ?? within a temperature range from 300 to 10 K. We found that the saturation of the subthreshold swing restricts further ??? scaling. However, we also found that under conditions T≦ 100 K and across different technology nodes, there exist optimal ? ?? ? values that effectively enhance the power efficiency of the devices, thereby improving their performance at low temperatures. To deepen our understanding, we established a fitting model to extract the band tail parameter. This model enables us to conduct in depth analysis across different technology nodes and reveals that the interface states follow a Gaussian distribution that varies with temperature. These findings will provide crucial references and guidance for future designs and optimizations of low temperature applications.

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