隨著人工智慧（AI）、物聯網（IoT）、高效能運算（HPC）及邊緣運算等技術快速發展，現代電子元件對高運算效能與低功耗操作的需求日益提升。然而，傳統矽基金屬氧化物半導體場效電晶體（metal–oxide–semiconductor field-effect transistor, MOSFET）隨著元件持續微縮，逐漸受到短通道效應、漏電流增加及次臨界擺幅（subthreshold swing, SS）60 mV/dec 熱力學極限的限制，使供應電壓與功耗難以進一步降低。近年來，具負電容效應（negative capacitance, NC）的鐵電 Hf0.5Zr0.5O2（HZO）因具有 CMOS 相容性及奈米尺度下仍可維持鐵電性的優勢，被視為實現低功耗電晶體的重要候選材料。此外，二維過渡金屬二硫族化物（2D transition metal dichalcogenides, 2D TMDs）中的 WSe2 具有原子級厚度、優異的靜電控制能力及良好的載子傳輸特性，適合作為下一世代低功耗電晶體通道材料。然而，HZO 與 WSe₂ 整合過程中仍可能面臨介面缺陷（如氧空缺）及費米能階釘扎等問題，進而影響載子注入效率與元件穩定性。
為降低 HZO 薄膜於重複乾式轉移過程中的機械損傷，並提升製程效率與量測一致性，本研究提出一種結合懸浮式（freestanding）HZO 薄膜轉移製程與乾式轉移（dry transfer）二維材料的元件整合策略。預先於基板上設計局部閘極陣列（local gate array）， HZO 薄膜轉移後，自陣列中選取一個局部閘極製作 WSe₂ 電晶體，而周圍其他局部閘極則分別製作金屬–絕緣體–金屬（MIM）電容及絕緣體–金屬（IM）結構以進行 PFM 、 SSPFM 等鐵電特性量測，藉此直接驗證 HZO 薄膜於完整元件製程後仍維持良好的鐵電特性。此外，於 HZO 與 WSe₂ 之間引入六方氮化硼（hBN）作為凡得瓦緩衝層，以降低介面缺陷、改善異質結構介面品質，並調控金屬接觸特性。透過光激發光譜（photoluminescence, PL）、原子力顯微鏡（atomic force microscopy, AFM）、壓電響應力顯微鏡（PFM）及溫度依賴電性量測，結合 Arrhenius 分析，以探討有效蕭特基能障與載子傳輸機制，並結合 PFM 結果探討鐵電耦合行為。
實驗結果顯示， HZO 薄膜於轉移製程後仍維持良好的鐵電特性，而 hBN 緩衝層可有效改善 HZO/WSe₂ 異質結構之介面品質，抑制介面缺陷造成的載子捕捉行為，並改善元件穩定性及載子注入特性。此外，本研究透過串聯電容模型分析，指出適當降低 hBN 厚度可改善 HZO 與 WSe2 間的電容匹配（capacitance matching）及靜電耦合。因此，未來若進一步最佳化 hBN 厚度，預期可在維持優異介面品質的同時兼顧穩定負電容操作，有望實現低功耗二維負電容電晶體。

Low-power transistors are essential for next-generation electronic systems, including artificial intelligence (AI), the Internet of Things (IoT), high-performance computing (HPC), and edge computing. However, conventional silicon-based metal–oxide–semiconductor field-effect transistors (MOSFETs) are fundamentally limited by severe short-channel effects, increased leakage current, and the thermionic subthreshold swing (SS) limit of 60 mV/dec, restricting further supply-voltage scaling and power reduction. Recently, ferroelectric hafnium zirconium oxide (Hf₀.₅Zr₀.₅O₂, HZO), owing to its negative capacitance (NC) effect, CMOS compatibility, and robust ferroelectricity at the nanoscale, has emerged as a promising candidate for low-power transistor applications. In addition, two-dimensional transition metal dichalcogenides (2D TMDs), particularly tungsten diselenide (WSe₂), possess an atomically thin body, excellent electrostatic controllability, and favorable carrier transport properties, making them attractive channel materials for next-generation low-power transistors. Nevertheless, interface defects (e.g., oxygen vacancies) and Fermi-level pinning at the HZO/WSe₂ interface remain major challenges that degrade carrier injection efficiency and device stability.
To minimize mechanical damage to HZO thin films caused by repeated dry-transfer processes while improving fabrication efficiency and measurement consistency, this study proposes a device integration strategy that combines freestanding HZO thin-film transfer with the dry transfer of two-dimensional materials. A local gate array was pre-patterned on the substrate prior to HZO transfer. After transferring the HZO thin film, one local gate was selected for WSe₂ field-effect transistor (FET) fabrication, while the surrounding local gates were utilized to fabricate metal–insulator–metal (MIM) capacitors and insulator–metal (IM) structures for ferroelectric characterization using piezoresponse force microscopy (PFM) and switching spectroscopy piezoresponse force microscopy (SSPFM). This design directly verifies that the HZO thin film retains its ferroelectric properties after the complete device fabrication process. Furthermore, a hexagonal boron nitride (hBN) layer was inserted between HZO and WSe₂ as a van der Waals buffer layer to suppress interface defects, improve the heterostructure interface quality, and modulate the metal–semiconductor contact characteristics. Photoluminescence (PL), atomic force microscopy (AFM), piezoresponse force microscopy (PFM), temperature-dependent electrical measurements, and Arrhenius analysis were employed to investigate the effective Schottky barrier and carrier transport mechanisms, while the PFM results were further correlated with the ferroelectric coupling behavior.
The experimental results demonstrate that the transferred HZO thin film retains excellent ferroelectric properties after the complete fabrication process. The hBN buffer layer effectively improves the interface quality of the HZO/WSe₂ heterostructure, suppresses carrier trapping induced by interface defects, and enhances both device stability and carrier injection characteristics. Furthermore, based on a series-capacitance model, this study demonstrates that appropriately reducing the hBN thickness can improve the capacitance matching and electrostatic coupling between the HZO layer and the WSe₂ channel. Therefore, by further optimizing the hBN thickness, stable negative-capacitance operation can be achieved while maintaining excellent interface quality, providing a promising pathway toward the realization of low-power two-dimensional negative-capacitance transistors.

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