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研究生: 黃柏暄
Huang, Po-Hsuan
論文名稱: 具資料完整性驗證功能之運算型儲存裝置設計
Design of an In-Storage Processing Device with Data Integrity Verification Capability
指導教授: 侯廷偉
Hou, Ting-Wei
學位類別: 碩士
Master
系所名稱: 工學院 - 工程科學系
Department of Engineering Science
論文出版年: 2025
畢業學年度: 113
語文別: 中文
論文頁數: 59
中文關鍵詞: 儲存裝置內運算雜湊函式資料可用性
外文關鍵詞: In-Storage Processing, Hash Function, Data Availability
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  • 隨著嵌入式系統與智慧邊緣應用的快速發展,資料儲存的安全性與可靠性日益重要。傳統的資料驗證與修復機制多仰賴主機端運算資源進行處理,不僅增加系統延遲,也提高資料搬移的成本與風險。為解決此問題,本研究基於儲存裝置內運算(In-Storage Processing, ISP)概念,於雙核心嵌入式平台上實作一套結合安全雜湊演算法(SHA)與多副本資料備援之資料完整性驗證與自動修復機制。
    本系統採用雙核心異質架構,其中一顆核心作為系統處理器,運行 Linux 作業系統,負責接收主機端命令,並將資料與其對應的 SHA 雜湊值一併傳送至 ISP 處理核心。系統處理器在傳送資料前,先以 SHA-256 或 SHA-512 進行雜湊計算,並將所得雜湊值作為資料的數位簽章(Digital Signature),與原始資料一同儲存於三個獨立儲存區域中,實現多副本備援架構,以提升資料可用性。
    本研究以人臉辨識應用為例,針對每筆人臉特徵向量計算對應的 SHA 雜湊值,並將其作為資料完整性驗證之依據。透過此方式,可有效判斷特徵資料是否遭到毀損,即使在多副本儲存架構下,仍能確保每筆人臉特徵的一致性與完整性,有效提升生物特徵資料的可信度。
    在資料讀取階段,系統會針對三份副本進行雜湊驗證,若發現某一副本異常,將根據其餘兩份資料進行比對,並執行自動化修復。另一方面,ISP 核心則以 Bare-metal 韌體方式運行,負責對本地 Flash 中的單一副本執行定期資料完整性檢查,透過重新計算 SHA-256 雜湊值與既有記錄進行比對,協助系統及早偵測潛在資料異常。
    實驗結果顯示,在 無毀損情境下,對 5000 筆人臉特徵向量進行 SHA-256/512 驗證平均耗時僅 943/873 ms。在 模擬單一副本毀損情境下,本研究針對 0 至 1000 筆毀損資料,以每 200 筆為區間進行測試,結果顯示系統能於 1400至2000 ms 的時間內完成修復。

    With the growth of embedded systems and edge applications, ensuring secure and reliable data storage has become increasingly important. Traditional verification and recovery rely on host-side processing, causing higher latency and data movement overhead. This work presents an In-Storage Processing (ISP) approach on a dual-core embedded platform, integrating Secure Hash Algorithms (SHA-256/512) with multi-replica redundancy for data integrity verification and automatic recovery. One core, running Linux, handles host communication and hash computation, while the bare-metal ISP core performs periodic integrity checks on local Flash. Using facial recognition as a case study, the system verifies and repairs corrupted replicas by comparing hash values across three copies, ensuring data consistency and improving availability of biometric data.

    摘要 I Extended Abstract II 致謝 IX 目錄 X 表目錄 XII 圖目錄 XIII 第一章 緒論 1 1.1 研究動機 1 1.2 研究目的 2 1.3 研究貢獻 2 第二章 文獻探討 3 2.1 儲存裝置內運算(In-storage Processing) 3 2.2 雜湊函式 5 2.2.1 雜湊函式介紹 5 2.2.2 SHA-256及SHA-512運作原理 6 2.3 固態硬碟資料可用性(Data Availability)與容錯機制 10 2.3.1 故障檢測機制(Fault Detection) 10 2.3.2 錯誤更正碼(Error Correction Codes) 11 2.3.3 資料冗餘機制(Redundancy Mechanisms) 12 第三章 系統設計與實作 16 3.1 Sylph系統架構 16 3.2 移植雜湊函式及實作 19 3.2.1 雜湊函式之平台移植 19 3.2.2 雜湊函式之平台實作 22 3.3 A35核心與M4核心間資料交換 25 3.3.1 基於 RPMsg v2 架構之通訊機制與改良實作 26 第四章 研究成果與討論 31 4.1 實驗規格與環境 31 4.2 實驗設計 32 4.2.1 雜湊演算法效能測試設計 34 4.2.2 多副本儲存驗證與修復情境模擬 35 4.2.3 跨裝置間資料恢復 36 4.2.4 Cortex-M4 單副本自我檢查設計 37 4.2.5 RPMsg機制改善結果 38 4.3 問題與討論 39 第五章 結論與未來展望 40 5.1 結論 40 5.2 未來展望 40 參考文獻 42

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