在現今多樣化的封裝架構下，本論文旨於研究一種封裝方式，兼具低成本、高性能、低耗電、容易設計...等諸多優勢，架構於既有的封裝體系下做些許的改變。該封裝方式藉由第一銲點打柱狀金凸塊取代電鍍凸塊或傳統打金線於晶片上，接著採用覆晶封裝方式完成低腳數封裝體。該封裝體經過了可靠度試驗，經失效性分析後仍有不錯的表現，因此才撰寫本文發表。本論文陳述編排如下，在第一章節簡述研究背景以及動機，藉此展開為何研究此項技術。在第二章節針對應用於本項技術之相關基礎理論加以闡述。在第三章節針對本研究實作部份逐一說明，並在第四章節該試片經一些測試後的結果，最後在第五章節做總結，並敘述後續研究方向。

SUMMARY
For DRAM packages, flip chip (FC) type package using gold stud bump (GSB) is more flexible than wire bond (WB) type one using bonding wires in electrical performance. The feasibility was proven by a series of work, including 2D substrate layout, 3D full wave simulation, package fabrication, reliability test, failure analysis, time domain and frequency domain measurement. From this study low pin count packages using GSB flip chip bonding had the following advantages such as low cost, large capacity, low power and design enabled. Moreover, from electrical performance, GSB packages have better electrical performance than traditional WB packages.
*Author **Advisor
Key Words: DRAM package, Flip Chip package, Gold stud bump.

INTRODUCTION
An outline of the next generation technologies is comprehensively shown on 2018 Consumer Electronics Show (CES). With advancement and development in artificial intelligence, 5G connectivity, autonomous driving, virtual reality, intelligent personal assistant and so on where a great number of infrastructure in semiconductor field including chips and packages have to meet all requirements for the next generation consumer products. Moreover, the importance of packages to the whole of consumer products is steadily increasing, and different packages are suitable for different consumer products. For DRAM package application, the WB type packages will not meet the operation frequency requirement sooner or later, therefore, flip chip type is a promising candidate for the next generation DRAM packages. It is well-known that the key processing steps of flip chip are bonding and dispensing. The major difference between this study and other literature is the pad location where central pads vs. peripheral pads. Based on those reasons mentioned above, the detail description of this study is presented in each chapter. The backgrounds and motives are described in Chapter 1. In Chapter 2, those related theories has been explained. Then a processing procedure is presented in chapter 3 and results after reliability test and failure analysis are shown in chapter 4. Finally, a total summary and future work are shown in chapter 5. From this study, GSB packages have better electrical performance than traditional WB packages.

MATERIALS AND METHODS
For readers to quickly understand this study, the material and method are introduced by chapters listed as follows.
In chapter 1, the background and the motive are described based on the development of consumer products followed by how to increase operation frequency for DRAM package using mature packaging technology.
In chapter 2, the developing history and processing flows of packages were introduced, then the electrical theories of packages were presented as an essential background, including transmission line with derived formula, impedance match, digital signals from time domain with Time Domain Reflectometry (TDR), and digital signals from frequency domain by network model with Vector Network Analyzers (VNA).
In chapter 3, how to design and co-simulate flip chip substrate by impedance match, 2D layout, and 3D full wave software were described followed by comparing different substrate layout where the best layout was chosen to manufacture. GSB bonding on die pads was developed and proceeded where GSB is the first bond during wire bonding processes. In early stages of this study, the reliability of GSB bonded on die pads was investigated and confirmed by cratering test, intermetallic Compound (IMC) and cross-section. During bonding processes, NCP dispensed on substrates and GSB bonded on die pads were prepared, then thermosonic flip chip bonding was followed. Furthermore, Scanning Acoustic Tomography (SAT), mechanical decapsulation and cross-section were followed to investigate and confirm the bonding interfaces. After flip chip bonding, molding, laser marking, ball mounting and IQC were followed. Finally, flip chip packages using GSB were manufactured.
In chapter 4, flip chip package with GSB were confirmed by electrical measurement where passed samples went through reliability test to meet industry standards by the existing reliability analysis, whereas the failed samples went through failure analysis. During the reliability analysis, Level-3 preconditioning, highly accelerated stress test (HAST), high temperature storage life test (HT-SLT), temperature cycling test (TCT) and pressure cooker test (PCT) were executed. The failed samples went through failure analysis by cross-section and SEM where bonding interfaces and unfilled area were carefully investigated.

RESULTS AND DISCUSSION
Time domain electrical performance was characterized by TDR where WB packages with the characteristic of large L is worse than GSB flip chip package with the characteristic of large C. The frequency domain electrical performance was characterized by VNA where 3dB cut off frequency of GSB flip chip packages is better than WB packages. If the lowest 3dB cut off frequency is the bottleneck of operation frequency of DRAM packages, then, from this study, 3dB cut off frequency of GSB (2.6GHz) is better than the one of WB (1.7GHz).

CONCLUSION
In this study, GSB for DRAM package has proven to be feasible from several aspect. (1)For appearance, there is no obvious difference except the molding window. (2)For package processes, Flip Chip is a mature technology. (3)For challenge, bonding at central pads without support at peripheral area was overcome. (4)For electrical interconnection, O/S test was passed. (5)For reliability analysis, it met industry standards. (6)For failure analysis, GSB had good interconnection between GSB on a chip and bond pads on a substrate. (7)For electrical performance, GSB packages have better electrical performance than traditional WB packages.

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