本論文主要研製24-GHz之低功耗壓控振盪器，以及24-與60-GHz高除數除五除頻器。24-GHz改良型電流再利用之壓控振盪器採用TSMC 0.18-μm CMOS製程，並使用電流再利用式之架構完成，而為了可進一步降低功率消耗並可具有不錯的相位雜訊值，採用了基極順向偏壓的技術，可有效降低功率消耗，並利用MIM電容與可變電容並聯，以提升共振腔之Q值，達到較低的相位雜訊值。24-及60-GHz直接注入式除五除頻器分別採用TSMC 0.18-μm CMOS與TSMC 90-nm CMOS製程，使用高除數除頻器可降低鎖相迴路的複雜度，利用注入之訊號與振盪器之四階諧波項進行混頻，並注入鎖定達成除五的功能。最後設計之90-nm 60-GHz改良式除五除頻器改善原除五除頻器面積過大的問題，使用stub並串聯電容至地的方式，以代替使用四分之一波長的open stub造成面積較大的問題，而其在鎖定範圍上亦具有不錯的表現。

This thesis presents the design of a 24-GHz CMOS low-power VCO, 24- and 60-GHz divide-by-5 frequency dividers for millimeter-wave communication application. A 24-GHz low-power current-reuse VCO is implemented by TSMC 0.18-μm CMOS process. The 24- and 60-GHz divide-by-5 frequency dividers, which use the modified parallel injection topology, are implemented by TSMC 0.18-μm and 90-nm CMOS process, respectively. Finally, a 90-nm CMOS 60-GHz modified divide-by-5 frequency divider is presented. It adopts the injection locked structure and uses a series capacitor connected with a stub to reduce the chip size. The good performance and FOM values of the designed frequency dividers are obtained.

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[52] 陳臆聰，24-GHz CMOS壓控振盪器與24-及60-GHz除頻器之研製，國立成功大學電腦與通信工程研究所碩士論文，民國九十八年。