本論文主要分成兩部分，第一部分為理論探討，主要介紹DS-UWB及MB-OFDM的LO訊號產生方式，並利用相位雜訊模型(Hajimiri’s model)，分析五種不同的VCO架構之相位雜訊表現，並在最後討論外來雜訊，如偏壓電流源及直流電源之雜訊對VCO的影響。
第二部分為使用TSMC 0.18-μm CMOS製程實現一個16-GHz的差動式考畢茲壓控振盪器、一個使用切換電容的3.5–4.5-GHz壓控振盪器、及一個1.3–1.365-GHz之三倍頻電路。在16-GHz差動式考畢茲壓控振盪器方面，由於在高頻VCO中，不易得到高的輸出功率，此設計特別著眼於其輸出功率。量測結果顯示，16-GHz PMOS差動式考畢茲 VCO輸出頻率為15.63–16.5 GHz，在16.5 GHz時，輸出功率約為–1 dBm，相位雜訊為–115 dBc/Hz@1MHz，主動埠消耗功率為12.6 mW，和已發表之論文相較，其輸出功率及相位雜訊均得到不錯的結果。而在3.5–4.5-GHz壓控振盪器方面，設計目標為輸出頻率需涵蓋MB-OFDM之mode 1中的三個頻率，故使用一個互補式交連耦合對VCO，以期能夠使用到可變電容的所有範圍，並且使用一組切換電容來達到較大的頻率可調範圍。量測結果顯示頻率偏移，但仍涵蓋到較低頻的兩個頻率，也做了詳細的討論。
最後在三倍頻電路方面，由於在DS-UWB系統中，基頻部分即可以提供一個1.3–1.365-GHz的訊號，故以RF部分的LO來說，只需一個三倍頻電路，即可產生3.9–4.095-GHz 之LO訊號以供mixer降頻使用，可以省去頻率合成器之使用。電路使用次諧波混波器及polyphase filter來實現，輸入之差動訊號先經過polyphase filter分成四相位訊號後，同時將差動訊號及四相位訊號輸入次諧波混波器的RF端及LO端，即可在IF端得到三倍頻率的諧波。此設計可以在低電壓(1-V)下操作，模擬結果顯示消耗電流為4 mA，三次諧波的轉換增益為–3 dB，二次諧波和基頻則得到不錯之壓抑效果，轉換增益分別為–18 dB及–24 dB。

This thesis has two main sections. The first section presents the study on the design of the LO signal generator for DS-UWB and MB-OFDM applications. The VCO topologies have also been discussed in this section. The second section describes the implementation of a 16-GHz PMOS differentially Colpitts VCO, a 3.5–4.5-GHz VCO, and a 1.3-GHz frequency tripler for UWB wireless RF transceiver.
For the ciucuit implementation, a 16-GHz CMOS differential Colpitts VCO fabricated with the TSMC 0.18-µm 1P6M process is presented. This VCO is composed of a PMOS transistor-pair core circuit and two source follower output buffers. In order to achieve a high frequency operation, the value of the inductor of the tank is reduced. The VCO can operate at 16.5 GHz, and the measured phase noise at 1-MHz offset is –115 dBc/Hz. The power consumption of the VCO core circuit is 12.6 mW. Compared with previous reported works, this VCO has a much higher output power of –0.9 dBm at 16.5 GHz. The 3.5–4.5-GHz CMOS VCO with switched capacitor is also fabricated with the TSMC 0.18-µm process. The VCO is composed of a complementary cross-coupled VCO and a pair of switch capacitor. The output frequency is 3.32–4.13 GHz. The power consumption of the VCO core circuit is 12.6 mW.
Moreover, in the proposal of the DS-UWB, the relationship between the chipping rate and the carrier frequencies is always multiple of three. Therefore, we only need to use a frequency tripler to generate the LO signal without using the frequency synthesizer. The frequency tripler is also fabricated with the TSMC 0.18 µm 1P6M process. The frequency tripler is composed of a sub-harmonic mixer and a polyphase filter. A 1.3–1.365-GHz differential input signal will be transferred to be a quadurature signal by the polyphase filter. The original differential and the quadruature signal are applied to RF terminal and LO terminal of the sub-harmonic mixer, individually. Therefore, the IF of the sub-harmonic mixer can output a 3.9-GHz signal that is the triple of 1.3 GHz. This design could operate under low dc voltage of 1 V. The simulated power consumption is only 4 mW, and the conversion gain of the third harmonic is –3 dB. The simulated suppression of the fundamental and the second harmonic is 15 and 20 dBc.

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