[1] Y. Ni, “Smart image sensing in CMOS technology,” IEE Proceedings - Circuits, Devices and Systems, vol. 152, no. 5, pp. 455–464, Oct. 2005.
[2] Z. Chen et al., “CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference,” in IEEE Journal of Solid-State Circuits, vol. 56, no. 6, pp. 1924-1935, June 2021.
[3] Y. -C. Chiu et al., “A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors,” in IEEE Journal of Solid-State Circuits, vol. 55, no. 10, pp. 2790-2801, Oct. 2020.
[4] X. Si et al., “A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors,” in IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 189-202, Jan. 2020.
[5] X. Si et al., “A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4172-4185, Nov. 2019.
[6] K. Bong, S. Choi, C. Kim, S. Kang, Y. Kim, and H.-J. Yoo, “14.6 a 0.62 mW ultra-low-power convolutional-neural-network face recognition processor and a CIS integrated with always-on Haar-like face detector,” 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017, pp. 248-249.
[7] T. -H. Hsu et al., “A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel,” in IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2516-2524, Aug. 2021
[8] T. -H. Hsu et al., “A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction,” in IEEE Journal of Solid-State Circuits, vol. 56, no. 5, pp. 1588-1596, May 2021.
[9] M. Kłosowski, Y. Sun, W. Jendernalik, G. Blakiewicz, J. Jakusz and S. Szczepański, “Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 9, pp. 3258-3262, Sept. 2023.
[10] M. Raghu et al. “Transfusion: Understanding transfer learning for medical imaging,” in Advances in Neural Information Processing Systems (NeurIPS), vol. 32, pp. 3342–3352, 2019.
[11] H. Cruz, H. -Y. Huang, C. -H. Luo and S. -Y. Lee, “A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS,” in IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 2, pp. 287-299, April 2017.
[12] D. -L. Lin, C. -C. Wang and C. -L. Wei, “Color Range Images Captured by a Four-Phase CMOS Image Sensor,” in IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 732-739, March 2011.
[13] 나종광, "카메라 현상에 대해서 알아보기,". Accessed: May 18, 2025. [Online], Available: https://blog.naver.com/PostView.nhn?blogId=doodoo1028&logNo=220020302103&photoView=0.
[14] Z. Gao, C. Yang, J. Xu, and K. Nie, “A dynamic range enhanced readout technique with a two-step TDC for high speed linear CMOS image sensors,” Sensors, vol. 15, no. 11, pp. 28224–28243, 2015.
[15] M. Mori, M. Katsuno, S. Kasuga, T. Murata and T. Yamaguchi, “A 1/4in 2M pixel CMOS image sensor with 1.75 transistor/pixel,” 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), San Francisco, CA, USA, 2004, pp. 110-111 Vol.1.
[16] Young Chan Kim et al., “1/2-inch 7.2MPixel CMOS Image Sensor with 2.25/spl mu/m Pixels Using 4-Shared Pixel Structure for Pixel-Level Summation,” 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2006, pp. 1994-2003.
[17] J. Ohta, Smart CMOS Image Sensors and Applications, 2nd ed. Boca Raton, FL, USA: CRC Press, 2020. [Online]. Available: https://doi.org/10.1201/9781315156255.
[18] M. Nagata, J. Funakoshi and A. Iwata, “A PWM signal processing core circuit based on a switched current integration technique,” in IEEE Journal of Solid-State Circuits, vol. 33, no. 1, pp. 53-60, Jan. 1998.
[19] S. Shishido, I. Nagahata, T. Sasaki, K. Kagawa, M. Nunoshita, and J. Ohta, “Demonstration of a low-voltage three-transistor-per-pixel CMOS imager based on a pulse-width-modulation readout scheme employed with a one-transistor in-pixel comparator,” in Proc. SPIE, vol. 6492, Electronic Imaging, San Jose, CA, USA, Jan. 2007, Art. no. 64920L.
[20] K. Kagawa, S. Yamamoto, T. Furumiya, T. Tokuda, M. Nunoshita, and J. Ohta, “A pulse-frequency-modulation vision chip using a capacitive feedback reset with an in-pixel 1-bit image processing,” in Proc. SPIE, vol. 6068, pp. 60680C-1–60680C-9, San Jose, CA, USA, Jan. 2006.
[21] W. Yang, “A wide-dynamic-range, low-power photosensor array,” Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94, San Francisco, CA, USA, 1994, pp. 230-231.
[22] S. G. Chamberlain and J. P. Y. Lee, “A novel wide dynamic range silicon photodetector and linear imaging array,” in IEEE Journal of Solid-State Circuits, vol. 19, no. 1, pp. 41-48, Feb. 1984.
[23] T. Kakumoto, S. Yano, M. Kusudaa, K. Kamon, and Y. Tanaka. “Logarithmic conversion CMOS image sensor with FPN cancellation and integration circuits,” J. Inst. Image Information & Television Eng, vol. 57, no. 8, pp. 1013–1018, Aug. 2003.
[24] O. Schrey, J. Huppertz, G. Filimonovic, A. Bussmann, W. Brockherde and B. J. Hosticka, “A 1K × 1K high dynamic range CMOS image sensor with on-chip programmable region of interest readout,” Proceedings of the 27th European Solid-State Circuits Conference, Villach, Austria, 2001, pp. 97-100.
[25] M. Sasaki, M. Mase, S. Kawahito and Y. Tadokoro, “A wide dynamic range CMOS image sensor with multiple short-time exposures,” SENSORS, 2004 IEEE, Vienna, Austria, 2004, pp. 967-972 vol.2.
[26] M. Schanz, C. Nitta, A. Bussmann, B. J. Hosticka and R. K. Wertheimer, “A high-dynamic-range CMOS image sensor for automotive applications,” in IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 932-938, July 2000.
[27] T. Hamamoto and K. Aizawa, “A computational image sensor with adaptive pixel-based integration time,” in IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 580-585, April 2001.
[28] Abbas El Gamal, “Lecture Notes 7 Fixed Pattern Noise,”. Accessed: May 18, 2025. [Online], Available: https://isl.stanford.edu/~abbas/ee392b/lect07.pdf.
[29] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching properties of MOS transistors,” in IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
[30] M. F. Snoeij, A. Theuwissen, K. Makinwa and J. H. Huijsing, “A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction,” 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2006, pp. 2014-2023.
[31] Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York, NY, USA: McGraw-Hill, 1987.
[32] K. H. Lundberg, Noise Sources in Bulk CMOS. [Online]. Available: http://web.mit.edu/klund/www/papers/UNP_noise.pdf
[33] [4]Sam Kench, “What is Rolling Shutter — Camera Shutter Effect Explained,”. Accessed: May 18, 2025. [Online], Available: https://www.studiobinder.com/blog/what-is-rolling-stutter/.
[34] S. Lauxtermann, “A. Lee, J. Stevens, and A. Joshi. Comparison of Global Shutter Pixels for CMOS Image Sensors.” In Int’l Image Sensor Workshop, pages 82–85, Ogunquit, Maine, USA, June 2007.
[35] M. Kobayashi et al., “A 1.8e −rms Temporal Noise Over 110-dB-Dynamic Range 3.4 μm Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter,” in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 219-228, Jan. 2018.
[36] W. J. Chiang, H. C. Chen, and Y. C. King, “Photodiode model for CMOS image sensor SPICE simulation,” in Proc. Int. Conf. Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 2006.
[37] M. -W. Seo, S. Kawahito, K. Kagawa and K. Yasutomi, “A 0.27e-rms Read Noise 220-μV/e-Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process,” in IEEE Electron Device Letters, vol. 36, no. 12, pp. 1344-1347, Dec. 2015
[38] S. Kawahito, S. Suh, T. Shirei, S. Itoh, and S. Aoyama, “Noise reduction effects of column-parallel correlated multiple sampling and source follower driving current switching for CMOS image sensors,” in Proc. Int. Image Sensor Workshop, 2009, pp. 320–323.
[39] S. Kleinfelder, SukHwan Lim, Xinqiao Liu and A. El Gamal, “A 10000 frames/s CMOS digital pixel sensor,” in IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 2049-2059, Dec. 2001.
[40] C. Posch, D. Matolin and R. Wohlgenannt, “A QVGA 143 dB Dynamic Range Frame-Free PWM Image Sensor With Lossless Pixel-Level Video Compression and Time-Domain CDS,” in IEEE Journal of Solid-State Circuits, vol. 46, no. 1, pp. 259-275, Jan. 2011.
[41] X. Zhong, Q. Yu, A. Bermak, C.-Y. Tsui, and M.-K. Law, “A 2PJ/Pixel/Direction MIMO processing based CMOS image sensor for omnidirectional local binary pattern extraction and edge detection,” in Proc. IEEE Symp. VLSI Circuits, Honolulu, HI, USA, Jun. 2018, pp. 247–248.
[42] Ka Nang Leung and P. K. T. Mok, “A sub-1-V 15-ppm//spl deg/C CMOS bandgap voltage reference without requiring low threshold voltage device,” in IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 526-530, April 2002.
[43] C. Jansson, K. Chen and C. Svensson, “Linear, polynomial and exponential ramp generators with automatic slope adjustment,” in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 41, no. 2, pp. 181-185, Feb. 1994.
[44] S. M. Gowda, H. Shin, H. Wong, P. Xiao, and J. Yang, “Correlated double sampling with up/down counter,” US patent 5,877,715, published Mar. 1999, filed Jun. 1997, 1999.
[45] Y. Wang, S. Lee, and K. O. Kim, “Comparison of several ramp generator designs for column-parallel single slope ADCs,” in Proc. Int. Image Sensor Workshop (IISW), Bergen, Norway, Jun. 2009, Paper P24.
[46] S. -F. Yeh and C. -C. Hsieh, “Novel Single-Slope ADC Design for Full Well Capacity Expansion of CMOS Image Sensor,” in IEEE Sensors Journal, vol. 13, no. 3, pp. 1012-1017, March 2013.
[47] J. Choi, J. Shin, D. Kang and D. -S. Park, “Always-On CMOS Image Sensor for Mobile and Wearable Devices,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 130-140, Jan. 2016.
[48] H. Totsuka et al., “6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016, pp. 116-117.
[49] Q. Zhang, N. Ning, J. Li, Q. Yu, K. Wu and Z. Zhang, “A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors,” in IEEE Access, vol. 8, pp. 172467-172480, 2020.
[50] M. R. Elmezayen, B. Wu and S. U. Ay, “Single-Slope Look-Ahead Ramp ADC for CMOS Image Sensors,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4484-4493, Dec. 2020.
[51] S. Yoshihara et al., “A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change,” in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2998-3006, Dec. 2006.
[52] H. -J. Kim, “11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors,” in IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 2132-2141, July 2021.
[53] Q. Liu, A. Edward, M. Kinyua, E. G. Soenen and J. Silva-Martinez, “A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques,” in IEEE Journal of Solid-State Circuits, vol. 52, no. 6, pp. 1591-1604, June 2017.
[54] M. F. Snoeij, A. J. P. Theuwissen, K. A. A. Makinwa and J. H. Huijsing, “Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors,” in IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2968-2977, Dec. 2007.
[55] S. Lim, J. Lee, D. Kim and G. Han, “A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs,” in IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 393-398, March 2009.
[56] J. Lee et al., “High frame-rate VGA CMOS image sensor using non-memory capacitor two-step single-slope ADCs,” IEEE Transactions on Circuits and Systems I: Reg. Papers, vol. 62, no. 9, pp. 2147-2155, Sept. 2015.
[57] S. -Y. Park and H. -J. Kim, “CMOS image sensor with two-step single-slope ADC using differential ramp generator,” IEEE Transactions on Electron Devices, vol. 68, no. 10, pp. 4966-4971, Oct. 2021.
[58] Q. Zhang, N. Ning, Z. Zhang, J. Li, K. Wu and Q. Yu, “A 12-bit two-step single-slope ADC with a constant input-common-mode level resistor ramp generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 5, pp. 644-655, May 2022.
[59] I. Park, C. Park, J. Cheon and Y. Chae, “A 76mW 500fps VGA CMOS image sensor with time-stretched single-slope ADCs achieving 1.95e- random noise,” 2019 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 100-102.
[60] B. Provost and E. Sanchez-Sinencio, “On-chip ramp generators for mixed-signal BIST and ADC self-test,” in IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 263-273, Feb. 2003.
[61] R. S. Prasobh Sankar, L. Asish and B. Bhuvan, “Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations,” 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Bangkok, Thailand, 2019, pp. 257-260.
[62] C.-C. Wang, A study of CMOS technologies for image sensor applications, Ph.D. dissertation, Dept. of Electrical Engineering, Massachusetts Institute of Technology, USA, 1969. [Online]. Available: https://dspace.mit.edu/handle/1721.1/8214.