在半導體產業界，自2000年銅導線開始量產，鉭金屬或鉭金屬化合物已廣泛應用在銅導線的擴散阻障層(Diffusion barrier layer)。歷經過數個技術世代的交替，配合著不同的製程技術演進，目前產業界仍持續地應用當中。尤其，以鉭/氮化鉭雙層結構材料(Ta-TaN bilayer)所製造出的低阻值擴散阻障層，得以與銅導線完整地進行技術整合，為其中最重要的關鍵。
在當前產業應用上，製造成本必要的考量因素，才能符合半導體業界大量量產上的需求。所以，在必須兼顧技術及成本雙重因素考量下，其挑戰相當大。
依據最新銅導線的之發展趨勢，在研究上已有實際使用釕金屬(Ru)或氮化釕(RuNx)做為擴散阻障層，主要具有超薄厚度之下仍保有低阻值的效能。應用此材料的靶材製造成本高，相對於使用在鉭金屬材料高約84倍。
本論文主要是在現有的技術上做研究，進一步延伸及深入探討。鉭/氮化鉭雙層結構材料透過氬離子轟擊的界面處理方法，所形成的鉭/界面處理-氮化鉭雙層結構材料改良材料，可以兼具所需的優良薄膜品質，包含：一、在嚴苛的高寬比之下，可以得到在好的階梯覆蓋率(good step coverage) ；二、為維持好的熱量條件(Thermal budget)的考量，在不加入製作溫度之下，所製造出的鉭/界面處理-氮化鉭雙層結構，得到低阻值擴散阻障層，可達接近於釕金屬材料的阻值； 三 、有效對整體銅導線製作做出整合，並可通過在產品上的電性及可靠性測試；四 、結合產量速度快的優點，整合擴散阻障層和銅晶種製作出的晶片，可達每小時至少完成70晶片產量。綜合以上所述的優點，在學術及產業的結合之下，完成實際在產品上做出應用。
經過研究氬離子轟擊的界面處理方法，最重要關鍵研究面向如下：第一、形成再濺鍍(Resputter, Resputtering) 過程，同時，可穩定引導出控制低阻值α相-鉭金屬的方法。第二、使用此再濺鍍方法，改善了薄膜沉積填洞能力，若不能調整到最佳化，易造成在溝槽(trench)角落區域產生出過度蝕刻的缺陷，這樣的現象會使銅原子擴散至介電層中，導致元件可靠度下降。在此研究中，找出沉積及再濺鍍的關係，透過參數調整可以定義出有效地製程調整方法。第三、運用高倍率顯微鏡(High Resolution TEM , HRTEM )檢查微觀結構，找出可以穩定形成鉭金屬α相原因，不僅可因應超薄阻障層厚度的趨勢，且透過實驗保留低阻值α相-鉭金屬，可延伸為下一世代阻障層結構設計。
更進一步來看，找出，其中本實驗發現在現有的半導體可常使用的鈦金屬以及鎢金屬材料，可以做為適合的產生低阻值α相-鉭金屬的基底材料。從微觀結構觀察之下，不僅在技術上能符合技術藍圖趨勢上的28~20奈米的要求條件，並且在製造成本上可以維持優勢。
綜合以上所述，本論文研究在具有製造成本的優勢下，使用氬離子轟擊的界面處理方法，其鉭/界面處理-氮化鉭雙層結構不僅符合薄厚度之下要求，並可達到低阻值的目標。此外，延伸出α相-鉭/鈦結構及α相鉭-鎢結構低阻值的材料，並可做為其他產品應用上的發展研究之重點。

When copper interconnect began to be mass produced in the semiconductor industry, Tantalum or Tantalum compounds has been widely applied as the most important diffusion barrier layer candidate in Copper interconnect. After several technological generations and being adopted for various manufacturing evolutionary stages, it is still in use. Specifically, the diffusion bilayer with Ta-TaN, which allows for well integration with copper interconnects, is the most critical technology.
In addition to technological advancement, the current semiconductor industry must also consider fabrication cost requirements in order that production can meet current demand. Meeting both technological and cost requirements present a major challenge on research and development.
According to the latest copper wire development trends, ruthenium (Ru) or ruthenium nitride (RuNx) as diffusion barrier layer for 20nm~28nm technology. That is mainly the low-resistivity performance under the ultra-thin thickness. Hoewever, the Ruthenium target cost of is higher than that of Tantalum metal about 84 times.
This paper will focus on developing a robust fabrication method to meet technological requirements while achieving cost competitiveness. It aims to find a breakthrough method to reach the low resistance under the thin-thickness. The key points of this research are as below: (1) The Ta-TaN bilayer, as the material candidate, is combined with optimized resputter fabricate methodology. The methodology provides conformality with good step coverage in the subsequent barrier and copper seed steps. (2) The method can fabricate without extra heat needed under low thermal budge condition. Besides, the Resputter fabrication acts as the treatment method to improve the interface between Ta-TaN to reach the low resistance requirement. (3) Effectively integrated overall copper interconnect production to get electriccal and reliability test on the product wafer; (4) Integrate the barrir layer/copper seed advantages and combine with production speed that up to at least 70 wafers per hour production. The points described above, under a combination of study and industry, to complete the actual product to make application.
The key points of this study of the interface Argon bombard treatment list as below (1) The Resputter process can be stable to guide a low resistance α phase - tantalum metal. (2) The resputter fabrication can improve the gap fill ability to get good step coverage; however, if the fabrication is not optimized, it is easy to produce over-etching phenomenon in the trench corner area. The defect will induce the copper diffuse and thus compromise device reliability. This study aims to find the deposition and resputter correlation and prevent this defect through process optimize. (3) This study will identify the Tantalum microstructure by high-magnification microscope (High Resolution TEM, HRTEM) and the stable α-phase formation factors. Besides, we also study the Titanium and Tungsten underlayer to enhance the stable low resistance α phase Tantalum produce. That can be effectively achieved so that low resistance is measured even under thinhickness to meet the requirements of trends of 28 to 20 nanometers copper interconnect Technology Roadmap under low cost on manufacturing.
The above, this study with use of argon ion bombardment interface approach combine the manufacturing cost advantages. The Ta/treated-TaN bilayer structure not only meets the requirements under the thin thickness, can reach the goal of the low resistance. Furthermore, Ta/Ti and Ta/W bilayer structure can prove low resistance under thin structure.It is the hope of the researcher can be used as the development of other products application.

[1] http://www.sematech.org/meetings/archives/3d/8964/pres/Cabral.pdf
[2] http://www.metalprices.com/FreeSite/metals/re/re.asp
[3] 陳君瑋，博士論文：“釕合金薄膜作為積體電路內連線系統中擴散阻障層/銅晶種層之應用與分析”，材料科學及工程研究所，成功大學，民國100年。
[4] R. Akolkar and U. Landau, J. Electrochem. Soc. ,151, C702 (2004).
[5] L.A. Clevenger, A. Mutscheller, J.M.E. Harper, C. Cabral, Jr., K. Barmak, J.Appl. Phys., 72, 15 (1992).
[6] C. S. Seet, B. C. Zhang, C. Yong. S. L. Liew, K. Li, L. C. Hsia, H. L. Seng, T. Osiposwicz, J. Sudijono, H. C. Zeng, J. B. Tan , J . Electrochem, Soc., 150, G766 (2003).
[7] G. S. Chen, S.T. Chen, S.C. Huang, H.Y. Lee Appl. Surf. Sci., 169, 353 (2001).
[8] S. P. Murarka, I. V. Verner, and R. J. Gutmann, Copper-Fundamental Mechanisms for Microelectronic Applications, Wiley Interscience, New York, 35 (2000).
[9] E. Klawuhn, G. C. D’Couto, K. A. Ashitiani, P. Rymer, M. A. Bibberger, and K. B. Levy, J. Vac. Sci. Technol. A 18 , 1546 (2000).
[10] J. J. Kelly, C. Tian, A. C. West, J. Electrochem. Soc., 146, 2540 (1999).
[11] H. B. Profijt, S. E. Potts, M. C. M. van de Sanden, and W. M. M. Kessels , J. Vac. Sci. Technol. A, 29, 050801 (2011).
[12] 曹榮志、劉繼文：“銅雙鑲嵌結構之漏電現象與防制方法” 電子月刊，九月號，第135-140頁，民國93年。
[13] W. Wang, J. Foster, N. Zimmerman, A. Wendt, J. H. Booske , N. Hershkowitz, Advanced Metallization and Interconnect System for ULSI Application , (1997).
[14] W. Wu, X. Duan, and J. Yuan IEEE Trans. Device Mater Rel. 3, 26 (2003).
[15] G. Raghavan, C. Chiang, P. B. Anders, S.Tzeng, R.Villasol, G.Vbai, M. Bohr, and D. B.Fraster, Thin Solid Films, 262, 168 (1995)
[16] D. Edelstein, C. Uzoh, C. Cabral Jr., P. Dehaven, P. Buchwalter, A. Simon, E. Cooney, S. Malhotra, D. Klaus, H. Rathore, B. Agarwala, D. Nguyen, in: Proceedings of IEEE International Interconnect Technol. Conf., Piscataway, NJ, 9 (2001).
[17] S. M. Rossnagel, J. Vac. Sci. Technol. B, 20, 2328 (2002).
[18] A. Jiang, A. Yohannan, N.O. Nnolim, T.A. Tyson, L. Axe, S.L. Lee and P. Cote, Thin Solid Films, 437, 116 (2003).
[19] Q. Xie, X.P. Qu, J.J. Tan, Y.L. Jiang, M. Zhou, T. Chen, and G.P. Ru, Appl. Surf. Sci., 253, 1666 (2006).
[20] K.L. Ou, W.F. Wu, C.P. Chou, S.Y. Chiou, and C.C. Wu, J. Vac. Sci. Technol. B, 20, 2154 (2002).
[21] K.H. Min, K.C. Chun and K.B. Kim, J. Vac. Sci. Technol. B, 14, 3263 (1996).
[22] G. B. Alers, R.T Rozbicki, G.J Harm, S.K. Kailasam, G.W. Ray, M Danek., Proceedings of the IEEE 2003 International Technology Conference , (2003)
[23] J. W. Lim, M. Mimura and M. Isshiki, Jpn. J. Appl. Phys., 43 8267 (2004).
[24 ] http://www.kla-tencor.com/metrology/rs-100.html
[25 ] C. Thomsen, H.T. Grahn, H.J. Maris, and J. Tauc, Phys. Rev., B 34, 4129 (1986).
[26 ] C. J. Morath, G. J. Collins, R. G. Wolf, R. J. Stoner, C. J. Morath, Solid State Technol., 40, 85 (1997).
[27 ] http://www.avsusergroups.org/tfug_pdfs/TFUG_07_2002_thinfilm.pdf
[28] 方信喬，博士論文：“電子顯微鏡研究矽太陽能電池背電極之形成與微觀結構”，材料科學及工程學系, 成功大學，民國100年。
[29] 林志成、林世明、李世元：“奈米量測技術－原子力顯微鏡在生物分子上之應用”，化學學刊，第六十七卷，第一期，83-91頁，民國98年。
[30] http://www.ch.ntu.edu.tw/~rsliu/solidchem/Report/Chapter6_report.pdf
[31] C. S. Seet, B. C. Zhang, C. Yong. S.L. Liew, K. Li, L.C. Hsia, H.L. Seng, T. Osiposwicz, J. Sudijono, H.C. Zeng, and J.B. Tan , J . Electrochem, Soc., 150, G766 (2003).
[32] H. Donohue, H. Gris, J. C. Yeoh, and K. Buchanan, Proceedings of the IEEE International Interconnect Technology Conference, 179 (2002). [33] P. Catania, J. P. Doyle, and J. J. Cuomo, J. Vac. Sci. Technol. A, 10, 3318 (1992).
[34] D. B. Hayden, D. R. Juliano, K. M. Green, D. N. Ruzic, C. A. Weiss, K.A. Ashtiani, and T. J. Licata, J. Vac. Sci. Technol. A, 16, 624 (1998).
[35] G. S. Chen, S.T. Chen, S.C. Huang, and H.Y. Lee, Appl. Surf. Sci., 169, 353 (2001).
[36] T. Tanaka and K. Kawabata, Thin Solid Films, 312, 135 (1998).
[37] D. W. Face and D.E. Prober, J. Vac. Sci. Technol. A, 5, 3408 (1987).
[38] J. H. Wang, L. J. Chen, Z. C. Liu, C. S. Hsung, W. Y. Hsieh, and T. R. Yew, J. Vac. Sci. Technol., B 20, 1522 (2002).
[39] M. Stavrev, D.Fischer, C. Wenzel, K. Drescher, and N. Mattern, Thin Solid Film, 307, 79 (1997).
[40] J. C. Tsao, C. P. Liu, Y. L. Wang, and K. W. Chen, J. Nanosci. Nanotechnol. 8, 2582 (2008).
[41] G. Raghavan, C. Chiang, P. B. Anders, S. Tzeng, R. Villasol, G. Vbai, M. Bohr, D. B. Fraster, Thin Solid Films, 262, 168(1995)
[42] E. M. Lee, W. C. Shin, Y. S. Choi, S. G. Yoon, J. Electrochem. Soc., 148, G611 (2001).
[43] L. Gladczuk, A. Patel, J. D. Demaree, and M. Sosnowski, Thin Solid Films, 476, 295 (2005).
[44] G. S. Chen, S.T. Chen, S. C. Huang, and H. Y. Lee, Appl. Surf. Sci. 169, 353 (2001).
[45] J. Chen, S. Parikh, T. Vo, S. Rengarajan, T. Mandewkar, P. Ding, L. Chen, and R. Mosely, Interconnect technology Conference, 185 (2002).
[46] N. Tu, J. Appl. Phys., 94, 5451 (2003).
[47] P. C. Andricacos, Interface, 8, 32 (1999).
[48] T. P. Moffat, J. E. Bonevich, W. H. Huber, A. Stanishevsky, D. R. Kelly, G. R. Stafford, D. Josell, J. Electrochem. Soc., 147, 4524 (2000).
[49] D. Josell, D. Wheeler, W. H. Huber, T. P. Moffat, Phys. Rev. Lett., 87, 016102 (2001).
[50] S. C. Chang, J. M. Shieh, B. T. Dai, M. S. Feng, J. Vac. Sci. Technol,. B 20, 2295 (2002).
[51] G. S. Chen, H. S. Tian , C.K. Lin , G. S. Chen , H. Y. Lee , J. Vac. Sci. Techno., A 22, 281 (2004).
[52] L. A. Clevenger, A. Mutscheller, J.M.E. Harper, C. Cabral, Jr., K. Barmak, J.Appl. Phys.,72, 4918 (1992).
[53] M. Ikeda, M. Murooka, and K. Suzuki, Jpn, J. Appl. Phys. 41, 3902 (2002).
[54] T. A. Panaioti, and S. G. Tsikh, Metal Sci and Heat Treat, 36, 301 (1994).
[55] P. Gregory, A. J. Bangay and T. L. Bird, Metallurgia, 71, 207 (1965).
[56] G. S. Chen, P. Y. Lee and S. T. Chen, Thin Solid Films, 353, 264 (1999).
[57] A. Jiang, T.A. Tyson, L.Axe, J. Phys.: Condens. Matter 17, 6111 (2005).
[58] L. G. Feinstein, R. D. Huttenmann, Thin Solid Films, 16, 129 (1973).
[59] S. L. Lee, D. Windover, Surf. Coat. Technol., 108, 65 (1998).
[60] R. Hoogeveen, M. Moske, H, Geisler, K. Samwer, Thin Solid Films, 275, 203 (1996).
[61] S. M. Rossnagel, I. C. Noyan, C. Cabral, Jr. J. Vac. Sci. Technol., B 20 (5), 2047 (2002).
[62] D. W Face, D. E. Prober, J. Vac. Sci. Technol., A 5 (6), 3408 (1987).
[63] C. Boudias and D. Monceau, CaRIne Crystallography 3.1 © (1989-1998). http://pro.wanadoo.fr/carine.crystallography.
[64] B. B. Burton, A. R. Lavoie, and S. M. George J. Electrochem. Soc. 155, D508 (2008).
[65] R. Akolkar, T. Indukuri, J. Clarke, T. Ponnuswamy, J. Reid, A.J. McKerrow, S. Varadarajan, Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International 1 (2011).
[66] J. Reid, A. McKerrow, S. Varadarajan, and G. Kozlowski, Solid State Technol. 53, 14 (2010).
[67] S. K. Cho, T. Lim, H. K. Lee and J. J. Kim J. Electrochem. Soc. 157, D187 (2010).
[68] S. Schaltin, N. R. Brook, L. Stappers, L. D’Urzo, H. Plank, G. Kothleitner, C.Gspan, K. Binnemans, J. Fransaer, J. Electrochem. Soc.158, D647 (2011).
[69] J. C. Tsao, Y. S. Wang, K.W. Chen, Y. L. Wang, “Capacitor structure in a semiconductor device”, US.2008/0251889 (2008).
[70] J. C. Tsao, M. C. Liao, P. Sun, K. W. Chen, “Alpha Tantalum Capacitor Plate”, U.S. Patent, No.7,969,708 (2009).