| 研究生: |
王銓慶 Wang, Chuan-Ching |
|---|---|
| 論文名稱: |
應用於MB-OFDM Mode-1 UWB接收機之CMOS壓控振盪器與頻率合成器的研製 Research on MB-OFDM Mode-1 CMOS Oscillators and Frequency Synthesizer for UWB Receiver |
| 指導教授: |
莊惠如
Chuang, Huey-Ru |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2007 |
| 畢業學年度: | 95 |
| 語文別: | 中文 |
| 論文頁數: | 112 |
| 中文關鍵詞: | 頻率合成器 、壓控振盪器 |
| 外文關鍵詞: | VCO, UWB, synthesizer |
| 相關次數: | 點閱:69 下載:3 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文主要分為三部份,第一部份主要是分析目前UWB兩大陣容的現況,以及現今新加入的DAA規範。第二部份則使用電路的觀點去分析相位雜訊,主要從Lesson’s相位雜訊模型出發,接著由單端平衡混波器開關的觀點開始,套用到振盪器上,用來解釋開關的閃爍雜訊如何透過頻率的轉移而惡化相位雜訊,然後解釋交連耦合對以及可變電容器的AM-to-FM conversion效應。最後則討論偏壓電流源之雜訊對振盪器的影響。第三部份則介紹所設計的三個電路。
第一顆電路為低電壓考畢茲振盪器內嵌注入鎖定式除頻器,在8-GHz CMOS壓控振盪器方面,採用TSMC 0.18-μm製程設計,此VCO架構採用轉導提升改良型的考畢茲振盪器搭配back-to-back varactor架構以達到低電壓及低相位雜訊的優勢。VCO可以正常操作在0.9 V低電壓之下,主動埠消耗功率為8.1 mW,在7.53 GHz振盪頻率之下,相位雜訊為-123.7 dBc/Hz @ 1 MHz,另外在注入鎖定式除頻器同樣的也是採用0.9 V低電壓之下,主動埠消耗功率為1.4 mW,經過除二電路之後的相位雜訊為-125.2 dBc/Hz @ 1MHz。第二顆晶片是內嵌單旁波帶混波器測試電路之四相位振盪器,輸出頻率,輸出功率與功率消耗均具有相當程度的準確性,在頻率偏差上不超過2 %,也正確的涵蓋到所希望設計的頻率。VCO主動埠消耗功率為16mW,在4.2 GHz振盪頻率之下,相位雜訊為-103.6dBc/Hz@1-MHz。第三顆晶片為應用於MBOA mode-1之頻率合成器,此頻率合成器量測結果在1.8 V的供應電壓之下功率消耗36.1 mW,相位雜訊在三個頻段皆低於-114 dBc/Hz @ 1MHz。本論文針對MB-OFDM的LO訊號產生方式,設計其相關之Mode-1頻率合成器及除頻器,未來可以更進一步將LO訊號產生方式整合於接收機中,以提升實用價值。
This thesis presents the research on CMOS RF oscillators and MB-OFDM Mode-1 frequency Synthesizer for UWB communication applications. The CMOS low voltage VCO are fabricated in TSMC standard 0.18m process. The 7.5 GHz Gm-boosted low voltage VCO exhibits an output frequency from 7.31 to 7.63 GHz, and a phase noise is –123.7dBc/Hz@1MHz.This VCO consumes 9mA from a 0.9-V supply. An injection-locked oscillator topology is integrated in this VCO, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The 7.5GHz divider consumes 1.35 mW.
The CMOS QVCO are fabricated in TSMC standard 0.18m process. The 4GHz Bottom-Series QVCO exhibits an output frequency from 3.93 to 4.4GHz, an output power of -7 dBm, and a phase noise is –103.6dBc/Hz@1MHz.The MB-OFDM Mode-1 CMOS frequency synthesizer fabricated in TSMC 0.18m process. This synthesizer provides 3 center frequencies, that is generated by single-sideband (SSB) mixing of the output frequency from an on-chip Phase Lock Loop (PLL) and another frequency derived from the PLL. Band switching time of less than 2.5 ns is realized by using a NMOS to switch the input signals of a SSB mixers. Operating at a 1.8 V supply, the unwanted sideband suppression for all the center frequencies are better than -28dBc.Power dissipation is 36.1 mW.
[1] S. Jose, “Design of RF CMOS power amplifier for UWB applications,” Thesis for Master of Science, Department of Electrical Engineering, Virginia Polytechnic Institute and State University, 2004.
[2] A. Batra et al., “Multi-band OFDM physical layer proposal for IEEE 802.15 task group 3a,” IEEE P802.15 Working Group for Wireless Personal Area Networks, March, 2004.
[3] http://www.neataiwan.com.tw/oldbooks3_view.asp?Ma_no=152&M_no=28&thisY=2005&thisM=12
[4] http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-776Spring-2005/CourseHome/index.htm
[5] H. Darabi and A. A. Abidi, “Noise in CMOS mixers: A simple physical model,” IEEE J. Solid-State Circuits, vol. 35, pp. 15-25, Jan. 2000.
[6] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[7] J. J. Real and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” in Custom IC Conf., Orlando, FL, pp. 569-572, 2000.
[8] B. Soltanian and P. Kinget, “AM-FM conversion by the active devices in MOS LC-VCOs and its effect on the optimal amplitude,” in IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 11-13, June 2006.
[9] E. Hegazi, A. Abidi, “Varactor characteristics,oscillator tuning curves, and AM-FM conversion,” IEEE J. of Solid-State Circuits vol. 38, no. 6, pp. 1033-1039, Jun. 2003.
[10] A. Jerng and C. G. Sodini, “The impact of device type and sizing on phase noise mechanisms,” IEEE J. of Solid-State Circuits, vol. 40, no. 2, pp. 360-369, Feb. 2005.
[11] S. Levantino, C. Samori, A. Bonfanti, S.L.J. Gierkink, A.L. Lacaita, and V. Boccuzzi, “Frequency dependenve on bias current in 5GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion,” IEEE J. of Solid-State Circuits, vol. 37, no. 8, pp. 1003-1011, Feb. 2002.
[12] 林曉彤,應用於無線通訊之CMOS射頻微機電開關及2-GHz/5-GHz壓控振盪器RFIC之研究,國立成功大學電機工程研究所碩士論文,民國九十三年。
[13] R. Aparicio and A. Hajimiri, “A noise-shifting differential colpitts VCO,” IEEE J. Solid-State circuits, vol. 37, no. 12, Dec. 2002.
[14] X. Li, S. Shekhar and D.J. Allstot, “Low-power gm-boosted LNA and VCO circuits in 0.18 μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12 pp. 2609-2619, Dec. 2005.
[15] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. of Solid-State Circuits, vol. 39, no. 7, pp. 1170-1174, July 2004.
[16] H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” in IEEE ISSCC Tech. Dig., pp. 412-413, Feb. 2001.
[17] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9 pp. 1415-1424, Sep. 2004.
[18] D. Ham and A. Hajimiri, “Concept and methods in optimization of integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, pp. 896-909, Jun. 2001.
[19] A. Bonfanti, S. Levantino, C. Samori and A. L. Lacaita, “A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs,” IEEE Trans. Circuits Syst, vol. 53, no. 3, pp. 481-488, Mar. 2006
[20] E. Hegazi, H. Sjőland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.
[21] P. Andreani and X. Wang, “On the phase-noise and phase-error performances of multiphase LC CMOS VCOs,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1883-1893, Nov. 2004.
[22] P. Andreani, A. Bonfanti, L. Romanò and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 1883-1893, Dec. 2002.
[23] B. Razavi et al., “A 0.13 μm CMOS UWB transceiver,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 216-217
[24] A. Aktas and M. Ismail, CMOS PLL ands VCOs for 4G Wireless, Kluwer Academic 2004.
[25] 高曜煌,射頻鎖相迴路IC設計,滄海書局,民國94年10月
[26] 郭信宏,應用於802.11 WLAN之2 GHz及5 GHz CMOS頻率合成器RFIC之設計研究,國立成功大學電機工程研究所碩士論文,民國九十三年。
[27] B. Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill 2002.
[28] J. Lee, “A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 566-573, Mar. 2002.
[29] 林展裕,應用於DS-UWB接收機之CMOS 4/8-GHz雙頻帶頻率合成器及射頻晶片的研究,國立成功大學電機工程研究所碩士論文,民國九十五年。
[30] B. Razavi, RF Microelectronics, Prentice Hall, 1997.
[31] X. Li, S. Shekhar D. J. Allstot, “Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2609-2619, Dec. 2005.
[32] S.-L. J, C.-F. Lee, “A low voltage and power LC VCO implemented with dynamic threshold voltage MOSFETS,” IEEE Microw. Compon. Lett., vol. 17, no. 5, May. 2007.
[33] K. Kwok and H C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 652-659, Mar. 2005.
[34] H. Jacobsson, M. Bao, L. Aspemyr, A. Mercha and G. Carchon, “Low Phase Noise sub-1 V Supply 12 and 18 GHz VCOs in 90 nm CMOS,” in Proc. IEEE RFIC Symp., pp. 573-576, Jun. 2007.