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研究生: 王銓慶
Wang, Chuan-Ching
論文名稱: 應用於MB-OFDM Mode-1 UWB接收機之CMOS壓控振盪器與頻率合成器的研製
Research on MB-OFDM Mode-1 CMOS Oscillators and Frequency Synthesizer for UWB Receiver
指導教授: 莊惠如
Chuang, Huey-Ru
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 112
中文關鍵詞: 頻率合成器壓控振盪器
外文關鍵詞: VCO, UWB, synthesizer
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  • 本論文主要分為三部份,第一部份主要是分析目前UWB兩大陣容的現況,以及現今新加入的DAA規範。第二部份則使用電路的觀點去分析相位雜訊,主要從Lesson’s相位雜訊模型出發,接著由單端平衡混波器開關的觀點開始,套用到振盪器上,用來解釋開關的閃爍雜訊如何透過頻率的轉移而惡化相位雜訊,然後解釋交連耦合對以及可變電容器的AM-to-FM conversion效應。最後則討論偏壓電流源之雜訊對振盪器的影響。第三部份則介紹所設計的三個電路。
    第一顆電路為低電壓考畢茲振盪器內嵌注入鎖定式除頻器,在8-GHz CMOS壓控振盪器方面,採用TSMC 0.18-μm製程設計,此VCO架構採用轉導提升改良型的考畢茲振盪器搭配back-to-back varactor架構以達到低電壓及低相位雜訊的優勢。VCO可以正常操作在0.9 V低電壓之下,主動埠消耗功率為8.1 mW,在7.53 GHz振盪頻率之下,相位雜訊為-123.7 dBc/Hz @ 1 MHz,另外在注入鎖定式除頻器同樣的也是採用0.9 V低電壓之下,主動埠消耗功率為1.4 mW,經過除二電路之後的相位雜訊為-125.2 dBc/Hz @ 1MHz。第二顆晶片是內嵌單旁波帶混波器測試電路之四相位振盪器,輸出頻率,輸出功率與功率消耗均具有相當程度的準確性,在頻率偏差上不超過2 %,也正確的涵蓋到所希望設計的頻率。VCO主動埠消耗功率為16mW,在4.2 GHz振盪頻率之下,相位雜訊為-103.6dBc/Hz@1-MHz。第三顆晶片為應用於MBOA mode-1之頻率合成器,此頻率合成器量測結果在1.8 V的供應電壓之下功率消耗36.1 mW,相位雜訊在三個頻段皆低於-114 dBc/Hz @ 1MHz。本論文針對MB-OFDM的LO訊號產生方式,設計其相關之Mode-1頻率合成器及除頻器,未來可以更進一步將LO訊號產生方式整合於接收機中,以提升實用價值。

    This thesis presents the research on CMOS RF oscillators and MB-OFDM Mode-1 frequency Synthesizer for UWB communication applications. The CMOS low voltage VCO are fabricated in TSMC standard 0.18m process. The 7.5 GHz Gm-boosted low voltage VCO exhibits an output frequency from 7.31 to 7.63 GHz, and a phase noise is –123.7dBc/Hz@1MHz.This VCO consumes 9mA from a 0.9-V supply. An injection-locked oscillator topology is integrated in this VCO, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The 7.5GHz divider consumes 1.35 mW.
    The CMOS QVCO are fabricated in TSMC standard 0.18m process. The 4GHz Bottom-Series QVCO exhibits an output frequency from 3.93 to 4.4GHz, an output power of -7 dBm, and a phase noise is –103.6dBc/Hz@1MHz.The MB-OFDM Mode-1 CMOS frequency synthesizer fabricated in TSMC 0.18m process. This synthesizer provides 3 center frequencies, that is generated by single-sideband (SSB) mixing of the output frequency from an on-chip Phase Lock Loop (PLL) and another frequency derived from the PLL. Band switching time of less than 2.5 ns is realized by using a NMOS to switch the input signals of a SSB mixers. Operating at a 1.8 V supply, the unwanted sideband suppression for all the center frequencies are better than -28dBc.Power dissipation is 36.1 mW.

    第一章 緒論 Introduction 1 1.1 超頻寬(UWB)研究背景與動機 1 1.2 UWB系統簡介 2 1.3 論文架構 4 第二章 低電壓考畢茲振盪器及直接注入鎖定式除頻器 5 2.1 8-GHz轉導提升差動式考畢茲壓控振盪器 5 2.1.1 本振盪器架構簡介 5 2.1.2 轉導提升考畢茲振盪器設計原理 7 2.2 直接注入鎖定式除二電路 12 2.2.1 基本注入鎖定式除頻器架構簡介 12 2.2.2 振盪器注入鎖定原理以及其應用 14 2.3 設計與製作流程 21 2.3.1 電路架構考量 21 2.3.2 振盪器電感選擇 21 2.3.3 可變電容器的選擇 24 2.3.4 主動電路寬度選擇 25 2.3.5 偏壓電路設計 27 2.3.6 注入鎖定除二電路設計 30 2.3.7 完整電路設計 31 2.3.8 模擬與量測結果 33 2.4 量測結果討論 37 第三章 內嵌單旁波帶混波器測試電路之四相位振盪器 39 3.1 四相位振盪器架構簡介 39 3.2 設計與製作流程 41 3.3 模擬與量測結果 45 3.4 量測結果討論 48 第四章 應用於MBOA mode-1 之頻率合成器 49 4.1 MB-OFDM之本地振盪源訊號產生方式 49 4.2 基本鎖相迴路雜訊源分析 52 4.3 鎖相迴路架構與系統規劃 58 4.4 鎖相迴路子電路設計 61 4.4.1 振盪器的設計與製作 61 4.4.2 相頻偵測器的設計與製作 65 4.4.3 電荷幫浦設計與製作 66 4.5 除頻器設計原理 70 4.5.1 高頻除二電路設計與製作 70 4.5.2 除五電路設計與製作 72 4.5.3 除三以及除八電路設計與製作 74 4.6 迴路濾波器設計與整體系統模擬 76 4.6.1 迴路濾波器原理簡介 76 4.6.2 整體系統模擬與量測結果 78 4.7 量測結果討論 81 第五章 結論 83 參考文獻 85 附錄A 相位雜訊之分析 89 A.1 Lesson’s相位雜訊模型介紹 89 A.2 單端平衡混波器開關的分析 95 A.3 振盪器的交連耦合對分析 99 A.4 可變電容器的非線性效應對相位雜訊的影響 105 A.5 電流源的雜訊對整體振盪器的影響 110

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