研究生: |
許介維 Hsu, Chieh-Wei |
---|---|
論文名稱: |
PBGA構裝體附加散熱器的熱傳分析 The study of heat transfer of PBGA package with Thermal Enchancement |
指導教授: |
吳俊煌
Wu, Gien-Huang |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 機械工程學系 Department of Mechanical Engineering |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 中文 |
論文頁數: | 79 |
中文關鍵詞: | PBGA構裝體 、散熱器 |
外文關鍵詞: | Plastic Ball Grid Array, Thermal Enchancement |
相關次數: | 點閱:72 下載:1 |
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由於封裝體朝向高散率,高I/O數,微小型化,所以強化散熱性能一直是很重要課題。本文使用ANSYS商用軟體, 建構詳細的網格, 在自然對流與強迫對流環境下,針對FC-PBGA封裝體裝配不同散熱器 進行精密的熱傳數值模擬分析,求解封裝體內溫度分佈。並進一步,比較它們的散熱性能。這個詳細的網格(detailed mesh) 含蓋熱通孔、錫球、與墊片、散熱銅層、防護罩、散熱器、PCB等重要元件, 使得網格更能接近實際封裝體, 使得模擬結果更準確。最後,針對影響封裝體散熱性能的各種變數(凸片長度、凸片厚度、凸片數目、支撐架厚度、凸片導熱係數、底板厚度與風速等因子)進行靈敏度分析。
The trend in microelectronics is toward increasing higher input/output, higher component density and higher electrical performance, which makes thermal enhancement to package performance an increasingly important issue. Under natural and forced convection conditions, three-dimensional (3D) finite element simulation is used to study the thermal performance of a flip-chip plastic ball grid array (FC-PBGA) assembly with various heatsink attached to the top surface of the assembly. The finite element model of this assembly is detail enough to include key packaging elements such as bump, solder balls, substrate, printed circuit board (PCB), vias and ground planes for both signal and power. 3D finite element simulation for temperature distribution is performed under varying values for the following variables: with/without heatsink/lid, with/without lid, fin length, fin thickness, fin number, Base height, heatsink conductivity and airflow speed. Thermal resistance is calculated to characterize and compare the thermal performance of the various package configurations.
1. ANSYS 9.0 Online Reference
2. Bennett Joiner, Tony Montes de Oca, “Thermal Performance of Flip
Chip Ball Grid Array Packages”, 18th IEEE SEMI-THERM Symposiu
m,2002.
3. C. B. Hwang, “Thermal design for flip chip on board in natural con
vection,” in Proc. 15th Semiconductor Thermal Meas. Manag. Symp.
(Semi-Therm), 1999, pp. 125-132.
4. Celik, Z. Z., Copeland, D., and Mertol, A., 1997, "Thermal Enhance
ment and Reliability of 40 mm EPBGA Packages With Interface Ma
terials," Proc. of 21st IEEE/CPMT Intl. Electronics Manufacturing Te
chnology Symp., Austin, TX, IEEE, Piscataway, NJ, pp. 376–385.
5. Ellison, G.N., “Thermal Computations for Electronic Equipment,” Van
Nostrand Reinhole Company, New York, 1989.
6. Frank P. Incropera, David P. DeWit “Fundamentals of Heat and Mas
s Transfer“, John Wiley & Sons, Inc., 2006
7. Hironori Matsushima, Shinji Baba, “Thermally Enhanced Flip-Chip B
GA with Organic Substrate”, IEEE, Electronic Components and Tech
nology Conference, 1998.
8. Lau, J.H., “High-Density PCB and Substrates,” Low Cost Flip Chip
Technologies.
9. Lee, T.-Y., 2000, “An Investigation of Thermal Enhancement on Flip
Chip Plastic BGA Packages Using CFD Tool,“ IEEE Trans.
Compon., Packag. Manuf. Technol., Part A, 23, pp. 481–489.
77
10.Mertol, A., ”Thermal Performance Comparison of High Pin Count C
avity-Up Enhanced Plastic Ball Grid Array (EPBGA) Packages,” IEE
E Transactions on Components, Packaging, and Manufacturing Techn
ology-Part B, Vol. 19, No. 2, pp. 427-443, 1996.
11.Msazumi. A, “Characterization of Chip Scale Packaging Materials”,
Microelectronics Reliability, Vol.39 Issue 9, pp.1365-1377., 1999.
12.Ramakrishna, K., Lee, T. -y. T., “Prediction of Thermal Performance
of Flip Chip Plastic Ball Grid Array (FC-PBGA) packages: effect o
f substrate physical design,” The Eighth Intersociety Conference on
Thermal and Thermo Mechanical Phenomena in Electronic Systems,
2002, pp. 528-537, 2002.
13.X. Hao, L. Qin, D. Yan, and S. Liu, “Thermal-Mechanical Stress A
nd Fatigue Failure Analysis Of A PBGA”, ICEPT2003, pp438-442.,
2003.
14.Zahn, B. A., “Optimizing Cost and Thermal Performance: Rapid
Prototyping of a High Pin Count Cavity-Up Enhanced Plastic Ball
Grid Array (EPBGA) Package, “Fifteenth IEEE SMEI-THERM Symp
osium, pp. 133-141, 1999.
15.