電源閘控(power gating)是一個有效能降低漏電流功耗的方法。此方法使用高臨界電壓(Vth)的電晶體來關掉電源，有效降低在待命的模式下的漏電流功耗，這種高臨界電壓的電晶體稱為睡眠電晶體。然而，這些睡眠電晶體受到偏壓不穩定效應(Bias Temperature Instability)的影響導致臨界電壓上升。較高的臨界電壓會減少電路的速度和可靠度。現今，許多睡眠電晶體的調整方法被提出，用來增加睡眠電晶體的寬度以維持電路的可靠度。然而，這些方法卻沒有考慮睡眠電晶體的偏壓不穩定效應，使得電路的可靠度出現問題。此外，電路本身也會受到偏壓不穩定效應的影響，因而降低電路的速度和產生可靠度的問題。在此篇研究中，我們提出兩種考慮偏壓不穩定效應的調整睡眠電晶體演算法來減少睡眠電晶體的總寬度。接著，我們也提出了放電矩陣(discharging matrix)的模型和相對應的演算法，用來計算流經睡眠電晶體的電流和降低計算放電矩陣的執行時間。實驗結果顯示，當只考慮睡眠電晶體的偏壓不穩定效應時，在90nm 製程下，提出的演算法可以減少25%~35%的睡眠電晶體面積。在32nm 製程下，提出的演算法可以減少13%~31%的睡眠電晶體面積。當同時考慮睡眠電晶體和電路的偏壓不穩定效應時，提出的演算法可以減少9%~31%的睡眠電晶體面積。此外，所提出的放電矩陣模型和演算法平均可以減少10%以上的執行時間。

Power gating is an effective way to reduce leakage power. This technique uses high Vth transistors, called sleep transistors, to turn off the power supply and significantly reduce leakage power in standby mode. However, these sleep
transistors suffer from the Bias Temperature Instability (BTI) effect, resulting in increased threshold voltage. The higher threshold voltage may decrease circuit speed and reliability. Currently, sleep transistor sizing techniques are proposed to increase sleep transistor sizes for circuit reliability. However, these techniques do not consider the BTI issue and may cause the circuit reliability issue to emerge. Furthermore, the circuit itself is also affected by the BTI effect, reducing the circuit speed and raising reliability issue. In this work, we propose two BTI-aware sleep transistor sizing algorithms to reduce the total width of sleep transistors. In addition, a discharging matrix model and its corresponding algorithm are also proposed to
calculate the current flowing through the sleep transistor to further reduce the runtime for updating discharging matrices. When only the BTI effect on sleep transistors is considered, the proposed algorithms can reduce total sleep transistor width by 25%~35% in 90nm technology and 13%~31% in PTM 32nm technology on average. When the BTI effect on both sleep and cluster transistors are considered,the proposed algorithms can further reduce 9%~31% total sleep transistor width. In addition, the discharging matrix model and its corresponding algorithm can reduce runtime by more than 10% on average.

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